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Superconducting Hyperdimensional Associative Memory Circuit for Scalable Machine Learning

Journal Article · · IEEE Transactions on Applied Superconductivity
Here we propose a generalized architecture for the first rapid-single-flux-quantum (RSFQ) associative memory circuit. The circuit employs hyperdimensional computing (HDC), a machine learning (ML) paradigm utilizing vectors with dimensionality in the thousands to represent information. HDC designs have small memory footprints, simple computations, and simple training algorithms compared to superconducting neural network accelerators (SNNAs), making them a better option for scalable SFQ machine learning (ML) solutions. The proposed superconducting HDC (SHDC) circuit uses entirely on-chip RSFQ memory which is tightly integrated with logic, operates at 33.3 GHz, is applicable to general ML tasks, and is manufacturable at practically useful scales given current SFQ fabrication limits. Tailored to a language recognition task, SHDC consists of ~ 2-20 M Josephson junctions (JJs) and consumes up to three times less power than an analogous CMOS HDC circuit while achieving 78-84% higher throughput. SHDC is capable of outperforming the state of the art RSFQ SNNA, SuperNPU, by 48-99% for all benchmark NN architectures tested while occupying up to 90% less area and consuming up to nine times less power. To the best of the authors' knowledge, SHDC is currently the only superconducting ML approach feasible at practically useful scales for real-world ML tasks and capable of online learning.
Research Organization:
Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
Sponsoring Organization:
Army Research Office (ARO); National Security Agency (NSA); USDOE Office of Science (SC)
Grant/Contract Number:
AC02-05CH11231
OSTI ID:
2326172
Journal Information:
IEEE Transactions on Applied Superconductivity, Journal Name: IEEE Transactions on Applied Superconductivity Journal Issue: 5 Vol. 33; ISSN 1051-8223
Publisher:
IEEECopyright Statement
Country of Publication:
United States
Language:
English

References (50)

Sparse Distributed Memory for Sparse Distributed Data book August 2022
Online learning: A comprehensive survey journal October 2021
Superconductor digital electronics: Scalability and energy efficiency issues (Review Article) journal May 2016
A review of cryogenic neuromorphic hardware journal February 2023
SuperMind: a survey of the potential of superconducting electronics for neuromorphic computing journal March 2022
Increasing integration scale of superconductor electronics beyond one million Josephson junctions journal June 2020
Experimental implementation of SFQ NDRO cells and 8-bit ADC journal March 1993
Hyper-Dimensional Computing Challenges and Opportunities for AI Applications journal January 2022
DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification conference January 2022
A Quantitative Study of Deep Learning Training on Heterogeneous Supercomputers conference September 2019
ImageNet: A large-scale hierarchical image database
  • Deng, Jia; Dong, Wei; Socher, Richard
  • 2009 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops (CVPR Workshops), 2009 IEEE Conference on Computer Vision and Pattern Recognition https://doi.org/10.1109/CVPR.2009.5206848
conference June 2009
Going deeper with convolutions conference June 2015
Cognitive Correlative Encoding for Genome Sequence Matching in Hyperdimensional System conference December 2021
Hyperdimensional Computing Encoding Schemes for Improved Image Classification conference November 2022
Hyperdimensional biosignal processing: A case study for EMG-based hand gesture recognition conference October 2016
Superconductive Single FlUX Quantum Logic Devices and Circuits: Status, Challenges, and Opportunities conference December 2020
Analogical mapping and inference with binary spatter codes and sparse distributed memory conference August 2013
Energy-efficient and high throughput sparse distributed memory architecture conference May 2015
A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications conference February 2018
Classification Using Hyperdimensional Computing: A Review journal January 2020
SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices conference October 2020
Zero Static Power Dissipation Biasing of RSFQ Circuits journal June 2011
Energy-Efficient Superconducting Computing—Power Budgets and Requirements journal June 2013
New AC-Powered SFQ Digital Circuits journal June 2015
AC-Biased Shift Registers as Fabrication Process Benchmark Circuits and Flux Trapping Diagnostic Tool journal June 2017
Simulation Analysis and Energy-Saving Techniques for ERSFQ Circuits journal August 2019
64-GHz Datapath Demonstration for Bit-Parallel SFQ Microprocessors Based on a Gate-Level-Pipeline Structure journal August 2021
Design of Discrete Hopfield Neural Network Using a Single Flux Quantum Circuit journal June 2022
GradientFlow: Optimizing Network Performance for Large-Scale Distributed DNN Training journal January 2019
A Regular Layout for Parallel Adders journal March 1982
Synergy of Dynamic Frequency Scaling and Demotion on DRAM Power Management: Models and Optimizations journal August 2015
SearcHD: A Memory-Centric Hyperdimensional Computing With Stochastic Training journal October 2020
High-Dimensional Computing as a Nanoscalable Paradigm journal September 2017
Classification and Recall With Binary Hyperdimensional Computing: Tradeoffs in Choice of Density and Mapping Characteristics journal December 2018
Faster R-CNN: Towards Real-Time Object Detection with Region Proposal Networks journal June 2017
Machine learning: Trends, perspectives, and prospects journal July 2015
A Robust and Energy-Efficient Classifier Using Brain-Inspired Hyperdimensional Computing conference August 2016
ImageNet classification with deep convolutional neural networks journal May 2017
Understanding Reduced-Voltage Operation in Modern DRAM Devices
  • Chang, Kevin K.; Yağlıkçı, Abdullah Giray; Ghose, Saugata
  • Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems https://doi.org/10.1145/3078505.3078590
conference June 2017
A case for superconducting accelerators conference April 2019
PipeDream: generalized pipeline parallelism for DNN training
  • Narayanan, Deepak; Harlap, Aaron; Phanishayee, Amar
  • SOSP '19: ACM SIGOPS 27th Symposium on Operating Systems Principles, Proceedings of the 27th ACM Symposium on Operating Systems Principles https://doi.org/10.1145/3341301.3359646
conference October 2019
A Computational Temporal Logic for Superconducting Accelerators
  • Tzimpragos, Georgios; Vasudevan, Dilip; Tsiskaridze, Nestan
  • Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems https://doi.org/10.1145/3373376.3378517
conference March 2020
SMART: A Heterogeneous Scratchpad Memory Architecture for Superconductor SFQ-based Systolic CNN Accelerators conference October 2021
Hdpg conference July 2022
Brain-inspired Cognition in Next-generation Racetrack Memories
  • Khan, Asif Ali; Ollivier, Sébastien; Longofono, Stephen
  • ACM Transactions on Embedded Computing Systems, Vol. 21, Issue 6 https://doi.org/10.1145/3524071
journal November 2022
A Survey on Hyperdimensional Computing aka Vector Symbolic Architectures, Part I: Models and Data Transformations journal December 2022
A Survey on Hyperdimensional Computing aka Vector Symbolic Architectures, Part II: Applications, Cognitive Models, and Challenges journal January 2023
A pythonic approach for rapid hardware prototyping and instrumentation conference September 2017
BrainFreeze: Expanding the Capabilities of Neuromorphic Systems Using Mixed-Signal Superconducting Electronics journal December 2021
Neural Networks with Quantization Constraints preprint January 2022