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A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

Conference ·
; ; ; ;  [1];  [2]
  1. Institute of Microelectronics, School of Computer Science and Techonology, Northwestern Polytechnical University, Xi'an (China)
  2. Institut Pluridiscipline Hubert Curien, CNRS/UDS/IN2P3, Strasbourg (France)

This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

Research Organization:
Institute of Electrical and Electronics Engineers - IEEE, 3 Park Avenue, 17th Floor, New York, N.Y. 10016-5997 (United States)
OSTI ID:
22531214
Report Number(s):
ANIMMA--2015-IO-157
Country of Publication:
United States
Language:
English

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