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Title: A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

Abstract

This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. Themore » gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)« less

Authors:
; ; ; ;  [1];  [2]
  1. Institute of Microelectronics, School of Computer Science and Techonology, Northwestern Polytechnical University, Xi'an (China)
  2. Institut Pluridiscipline Hubert Curien, CNRS/UDS/IN2P3, Strasbourg (France)
Publication Date:
Research Org.:
Institute of Electrical and Electronics Engineers - IEEE, 3 Park Avenue, 17th Floor, New York, N.Y. 10016-5997 (United States)
OSTI Identifier:
22531214
Report Number(s):
ANIMMA-2015-IO-157
TRN: US16V0417102155
Resource Type:
Conference
Resource Relation:
Conference: ANIMMA 2015: 4. International Conference on Advancements in Nuclear Instrumentation Measurement Methods and their Applications, Lisboa (Portugal), 20-24 Apr 2015; Other Information: Country of input: France; 9 refs.
Country of Publication:
United States
Language:
English
Subject:
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY; ALGORITHMS; AMPLIFIERS; ANALOG-TO-DIGITAL CONVERTERS; CADMIUM COMPOUNDS; CALIBRATION; DATA PROCESSING; DESIGN; DIGITAL FILTERS; ELECTRONS; GAIN; GAMMA RADIATION; INTEGRATED CIRCUITS; KEV RANGE; POSITRON COMPUTED TOMOGRAPHY; READOUT SYSTEMS; SEMICONDUCTOR DETECTORS; SIGNALS; ZINC TELLURIDES

Citation Formats

Gao, W., Yin, J., Li, C., Zeng, H., Gao, D., and Hu, Y. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector. United States: N. p., 2015. Web. doi:10.1109/ANIMMA.2015.7465547.
Gao, W., Yin, J., Li, C., Zeng, H., Gao, D., & Hu, Y. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector. United States. https://doi.org/10.1109/ANIMMA.2015.7465547
Gao, W., Yin, J., Li, C., Zeng, H., Gao, D., and Hu, Y. 2015. "A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector". United States. https://doi.org/10.1109/ANIMMA.2015.7465547.
@article{osti_22531214,
title = {A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector},
author = {Gao, W. and Yin, J. and Li, C. and Zeng, H. and Gao, D. and Hu, Y.},
abstractNote = {This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)},
doi = {10.1109/ANIMMA.2015.7465547},
url = {https://www.osti.gov/biblio/22531214}, journal = {},
number = ,
volume = ,
place = {United States},
year = {2015},
month = {7}
}

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