Loop parallelism on Tera MTA using SISAL
Conference
·
OSTI ID:224967
The difficulty of programming parallel computers has impeded their wide-spread use. The problems are caused by existing hardware and software tools. The software problems on shared-memory and vector computers can be solved by using deterministic high-performance functional languages like SISAL. Distributed-memory computers have even more obstacles than shared-memory parallel machines. Research indicates that multithreaded architectures can hide long latency of distributed memories and that they can solve the problems of locality. Tera`s MTA multiprocessor is based on the concept of multithreading and provides the programmer with a real shared-memory model. This paper investigates the performance of parallel loops written in SISAL and executed on the Tera MTA using the Livermore Loops benchmarks.
- Research Organization:
- Lawrence Livermore National Lab., CA (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- W-7405-ENG-48
- OSTI ID:
- 224967
- Report Number(s):
- UCRL-JC--122696; CONF-9511199--1; ON: DE96006767
- Country of Publication:
- United States
- Language:
- English
Similar Records
Proceedings: Sisal `93
An implementation of SISAL for distributed-memory architectures
Parallelization of a dynamic unstructured algorithm using three leading programming paradigms
Conference
·
Fri Oct 01 00:00:00 EDT 1993
·
OSTI ID:10123107
An implementation of SISAL for distributed-memory architectures
Thesis/Dissertation
·
Thu Jun 01 00:00:00 EDT 1995
·
OSTI ID:176572
Parallelization of a dynamic unstructured algorithm using three leading programming paradigms
Journal Article
·
Mon Jun 26 00:00:00 EDT 2000
· IEEE Transactions on Parallel and Distributed Systems
·
OSTI ID:776615