Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al{sub 2}O{sub 3} gate dielectric
- Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan (China)
Low-temperature atomic layer deposition (ALD) was employed to deposit Al{sub 2}O{sub 3} as a gate dielectric in amorphous In–Ga–Zn–O thin-film transistors fabricated at temperatures below 120 °C. The devices exhibited a negligible threshold voltage shift (ΔV{sub T}) during negative bias stress, but a more pronounced ΔV{sub T} under positive bias stress with a characteristic turnaround behavior from a positive ΔV{sub T} to a negative ΔV{sub T}. This abnormal positive bias instability is explained using a two-process model, including both electron trapping and hydrogen release and migration. Electron trapping induces the initial positive ΔV{sub T}, which can be fitted using the stretched exponential function. The breakage of residual AlO-H bonds in low-temperature ALD Al{sub 2}O{sub 3} is triggered by the energetic channel electrons. The hydrogen atoms then diffuse toward the In–Ga–Zn–O channel and induce the negative ΔV{sub T} through electron doping with power-law time dependence. A rapid partial recovery of the negative ΔV{sub T} after stress is also observed during relaxation.
- OSTI ID:
- 22489332
- Journal Information:
- Applied Physics Letters, Journal Name: Applied Physics Letters Journal Issue: 3 Vol. 108; ISSN APPLAB; ISSN 0003-6951
- Country of Publication:
- United States
- Language:
- English
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