Barrier reduction via implementation of InGaN interlayer in wafer-bonded current aperture vertical electron transistors consisting of InGaAs channel and N-polar GaN drain
- Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106 (United States)
This letter reports the influence of the added InGaN interlayer on reducing the inherent interfacial barrier and hence improving the electrical characteristics of wafer-bonded current aperture vertical electron transistors consisting of an InGaAs channel and N-polar GaN drain. The current-voltage characteristics of the transistors show that the implementation of N-polar InGaN interlayer effectively reduces the barrier to electron transport across the wafer-bonded interface most likely due to its polarization induced downward band bending, which increases the electron tunneling probability. Fully functional wafer-bonded transistors with nearly 600 mA/mm of drain current at V{sub GS} = 0 V and L{sub go} = 2 μm have been achieved, and thus demonstrate the feasibility of using wafer-bonded heterostructures for applications that require active carrier transport through both materials.
- OSTI ID:
- 22399139
- Journal Information:
- Applied Physics Letters, Vol. 106, Issue 2; Other Information: (c) 2015 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA); ISSN 0003-6951
- Country of Publication:
- United States
- Language:
- English
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