The fundamental downscaling limit of field effect transistors

Mamaluy, Denis; Gao, Xujiao

doi:10.1063/1.4919871

The fundamental downscaling limit of field effect transistors

Journal Article · Mon May 11 04:00:00 EDT 2015 · Applied Physics Letters

DOI:https://doi.org/10.1063/1.4919871· OSTI ID:22399060

Mamaluy, Denis; Gao, Xujiao ^[1]

Sandia National Laboratories, Albuquerque, New Mexico 87185-1322 (United States)

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.

OSTI ID:: 22399060

Journal Information:: Applied Physics Letters, Journal Name: Applied Physics Letters Journal Issue: 19 Vol. 106; ISSN APPLAB; ISSN 0003-6951

Country of Publication:: United States

Language:: English

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The fundamental downscaling limit of field effect transistors

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