The fundamental downscaling limit of field effect transistors

Mamaluy, Denis; Gao, Xujiao

doi:10.1063/1.4919871

Title: The fundamental downscaling limit of field effect transistors

Journal Article · Mon May 11 00:00:00 EDT 2015 · Applied Physics Letters

DOI:https://doi.org/10.1063/1.4919871· OSTI ID:22399060

Mamaluy, Denis; Gao, Xujiao ^[1]

Sandia National Laboratories, Albuquerque, New Mexico 87185-1322 (United States)

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.

Cite

Export

Save

OSTI ID:: 22399060

Journal Information:: Applied Physics Letters, Vol. 106, Issue 19; Other Information: (c) 2015 Author(s); Country of input: International Atomic Energy Agency (IAEA); ISSN 0003-6951

Country of Publication:: United States

Language:: English

References (18)

A simple quantum mechanical treatment of scattering in nanoscale transistors Venugopal, R.; Paulsson, M.; Goasguen, S. Journal of Applied Physics, Vol. 93, Issue 9 https://doi.org/10.1063/1.1563298	journal	May 2003
Iteration scheme for the solution of the two-dimensional Schrödinger-Poisson equations in quantum structures Trellakis, A.; Galick, A. T.; Pacelli, A. Journal of Applied Physics, Vol. 81, Issue 12 https://doi.org/10.1063/1.365396	journal	June 1997
Efficient self-consistent quantum transport simulator for quantum devices Gao, X.; Mamaluy, D.; Nielsen, E. Journal of Applied Physics, Vol. 115, Issue 13 https://doi.org/10.1063/1.4870288	journal	April 2014
Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition Gao-Bo, Xu; Qiu-Xia, Xu Chinese Physics B, Vol. 18, Issue 2 https://doi.org/10.1088/1674-1056/18/2/059	journal	February 2009
The physical limits of computing Frank, M. P. Computing in Science & Engineering, Vol. 4, Issue 3 https://doi.org/10.1109/5992.998637	journal	May 2002
CMOS scaling for sub-90 nm to sub-10 nm Iwai, H. . 17th International Conference on VLSI Design, 17th International Conference on VLSI Design. Proceedings. https://doi.org/10.1109/icvd.2004.1260899	conference	January 2004
Nanowatt logic using field-effect metal-oxide semiconductor triodes Wanlass, F.; Sah, C. 1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers https://doi.org/10.1109/isscc.1963.1157450	conference	January 1963
How much time does FET scaling have left? Mamaluy, D.; Gao, X.; Tierney, B. 2014 International Workshop on Computational Electronics (IWCE) https://doi.org/10.1109/iwce.2014.6865875	conference	June 2014
Limits to binary logic switch scaling-a gedanken model Zhirnov, V. V.; Cavin, R. K.; Hutchby, J. A. Proceedings of the IEEE, Vol. 9, Issue 11 https://doi.org/10.1109/jproc.2003.818324	journal	November 2003
The end of CMOS scaling Skotnicki, T.; Hutchby, J. A.; King, T. IEEE Circuits and Devices Magazine, Vol. 21, Issue 1 https://doi.org/10.1109/mcd.2005.1388765	journal	January 2005
Atomistic Modeling of Realistically Extended Semiconductor Devices with NEMO and OMEN Klimeck, Gerhard; Luisier, Mathieu Computing in Science & Engineering, Vol. 12, Issue 2 https://doi.org/10.1109/mcse.2010.32	journal	March 2010
Approaching Optimal Characteristics of 10-nm High-Performance Devices: A Quantum Transport Simulation Study of Si FinFET Khan, Hasanur R.; Mamaluy, Denis; Vasileska, Dragica IEEE Transactions on Electron Devices, Vol. 55, Issue 3 https://doi.org/10.1109/ted.2007.915387	journal	March 2008
Room-Temperature Operation of Silicon Single-Electron Transistor Fabricated Using Optical Lithography Sun, Yongshun; Singh, Navab IEEE Transactions on Nanotechnology, Vol. 10, Issue 1 https://doi.org/10.1109/tnano.2010.2086475	journal	January 2011
NEMO5: A Parallel Multiscale Nanoelectronics Modeling Tool Steiger, Sebastian; Povolotskyi, Michael; Park, Hong-Hyun IEEE Transactions on Nanotechnology, Vol. 10, Issue 6 https://doi.org/10.1109/tnano.2011.2166164	journal	November 2011
Influence of interface roughness on quantum transport in nanoscale FinFET Khan, H.; Mamaluy, D.; Vasileska, D. Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, Vol. 25, Issue 4 https://doi.org/10.1116/1.2748414	journal	January 2007
Irreversibility and heat generation in the computing process Landauer, R. IBM Journal of Research and Development, Vol. 44, Issue 1.2 https://doi.org/10.1147/rd.441.0261	journal	January 2000
Irreversibility and Heat Generation in the Computing Process Landauer, R. IBM Journal of Research and Development, Vol. 5, Issue 3 https://doi.org/10.1147/rd.53.0183	journal	July 1961
Nanowatt Logic Using Field-Effect Metal-Oxide Semiconductor Triodes Wanlass, F. M.; Sah, C. T. Semiconductor Devices: Pioneering Papers https://doi.org/10.1142/9789814503464_0081	book	March 1991

Cited By (5)

A Comparative Study on Scaling Capabilities of Si and SiGe Nanoscale Double Gate Tunneling FETs Bentrcia, Toufik; Djeffal, Fayçal; Ferhati, Hichem Silicon, Vol. 12, Issue 4 https://doi.org/10.1007/s12633-019-00190-w	journal	June 2019
Room temperature single electron transistor based on a size-selected aluminium cluster Zharinov, Vyacheslav S.; Picot, Thomas; Scheerder, Jeroen E. Nanoscale, Vol. 12, Issue 2 https://doi.org/10.1039/c9nr09467a	journal	January 2020
Channel Engineering for Nanotransistors in a Semiempirical Quantum Transport Model Wulf, Ulrich; Kučera, Jan; Richter, Hans Mathematics, Vol. 5, Issue 4 https://doi.org/10.3390/math5040068	journal	November 2017
Two-Dimensional MX2 Semiconductors for Sub-5 nm Junctionless Field Effect Transistors Peng, Bin; Zheng, Wei; Qin, Jiantao Materials, Vol. 11, Issue 3 https://doi.org/10.3390/ma11030430	journal	March 2018
The role of the Ge mole fraction in improving the performance of a nanoscale junctionless tunneling FET: concept and scaling capability Ferhati, Hichem; Djeffal, Fayçal; Bentrcia, Toufik Beilstein Journal of Nanotechnology, Vol. 9 https://doi.org/10.3762/bjnano.9.177	journal	June 2018

Similar Records

The fundamental downscaling limit of field effect transistors

Journal Article · Mon May 11 00:00:00 EDT 2015 · Applied Physics Letters · OSTI ID:22399060

Mamaluy, Denis; Gao, Xujiao

The ultimate downscaling limit of FETs.

Technical Report · Wed Oct 01 00:00:00 EDT 2014 · OSTI ID:22399060

Mamaluy, Denis; Gao, Xujiao; Tierney, Brian David

AlGaN High Electron Mobility Transistor for High-Temperature Logic

Journal Article · Sun Jan 29 00:00:00 EST 2023 · Journal of Microelectronics and Electronic Packaging · OSTI ID:22399060

Klein, Brianna Alexandra; Allerman, Andrew A.; Baca, Albert G.; +11 more

Related Subjects

71 CLASSICAL AND QUANTUM MECHANICS
GENERAL PHYSICS
COMPUTERIZED SIMULATION
DENSITY
ERRORS
MOSFET
OPERATION
ORIENTATION
PERFORMANCE
QUANTUM MECHANICS
SILICON
TEMPERATURE RANGE 0273-0400 K

Title: The fundamental downscaling limit of field effect transistors

Citation Formats

References (18)

Cited By (5)

Similar Records

Related Subjects