Improving the performance of organic thin film transistors formed on a vacuum flash-evaporated acrylate insulator

Journal Article · Mon Dec 02 04:00:00 EST 2013 · Applied Physics Letters

DOI:https://doi.org/10.1063/1.4839275· OSTI ID:22253905

Abbas, G. A.; Assender, H. E. ^[1]; Morrison, J. J.; Sanchez-Romaguera, V.; Yeates, S. G. ^[2]; Taylor, D. M. ^[3]

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1. Department of Materials, University of Oxford, Oxford OX1 3PH (United Kingdom)
2. School of Chemistry, University of Manchester, Manchester M13 9PL (United Kingdom)
3. School of Electronic Engineering, Bangor University, Bangor LL57 1UT (United Kingdom)

A systematic investigation has been undertaken, in which thin polymer buffer layers with different ester content have been spin-coated onto a flash-evaporated, cross-linked diacrylate gate-insulator to form bottom-gate, top-contact organic thin-film transistors. The highest device mobilities, ∼0.65 cm{sup 2}/V s and ∼1.00 cm{sup 2}/V s for pentacene and dinaphtho[2,3-b:2′,3′-f]-thieno[3,2-b]thiophene (DNTT), respectively, were only observed for a combination of large-grain (∼1–2 μm) semiconductor morphology coupled with a non-polar dielectric surface. No correlation was found between semiconductor grain size and dielectric surface chemistry. The threshold voltage of pentacene devices shifted from −10 V to −25 V with decreasing surface ester content, but remained close to 0 V for DNTT.

• OSTI ID: 22253905
• Journal Information: Applied Physics Letters, Journal Name: Applied Physics Letters Journal Issue: 23 Vol. 103; ISSN APPLAB; ISSN 0003-6951
• Country of Publication: United States
• Language: English

Related Subjects

36 MATERIALS SCIENCE
ACRYLATES
ADMINISTRATIVE PROCEDURES
DIELECTRIC MATERIALS
EQUIPMENT
ESTERS
GRAIN SIZE
MOBILITY
MORPHOLOGY
PENTACENE
PERFORMANCE
POLYCYCLIC SULFUR HETEROCYCLES
POLYMERS
SEMICONDUCTOR MATERIALS
SPIN
SURFACES
THIN FILMS
THIOPHENE
TRANSISTORS