Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays

Journal Article · Mon Dec 23 04:00:00 EST 2013 · Applied Physics Letters

DOI:https://doi.org/10.1063/1.4858955· OSTI ID:22253214

Han, X. L. ^[1]

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1. Institute of Electronics, Microelectronics and Nanotechnology, CNRS, Avenue Poincaré, 59652 Villeneuve d'Ascq (France)

Low-frequency noise is used to study the electronic transport in arrays of 14 nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around is sufficient in the sub-threshold voltage region to confine charges in the heart of the wire, and the extremely low noise level is comparable to that of high quality epitaxial layers. Although contact noise can already be a source of poor transistor operation above threshold voltage for few nanowires, nanowire parallelization drastically reduces its impact.

• OSTI ID: 22253214
• Journal Information: Applied Physics Letters, Journal Name: Applied Physics Letters Journal Issue: 26 Vol. 103; ISSN APPLAB; ISSN 0003-6951
• Country of Publication: United States
• Language: English

Related Subjects

77 NANOSCIENCE AND NANOTECHNOLOGY
ELECTRIC POTENTIAL
LAYERS
LENGTH
NOISE
QUANTUM WIRES
SILICON
TRANSISTORS