Microporous SiO{sub 2} with huge electric-double-layer capacitance for low-voltage indium tin oxide thin-film transistors

Journal Article · Mon Nov 30 04:00:00 EST 2009 · Applied Physics Letters

DOI:https://doi.org/10.1063/1.3271029· OSTI ID:21294491

Aixia, Lu; Jia, Sun; Jie, Jiang; Qing, Wan ^[1]

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1. Key Laboratory for Micro-Nano Optoelectronic Devices of Ministry of Education and State Key Laboratory of Chemo/Biosensing and Chemometrics, Hunan University, Changsha 410082 (China)

Electric-double-layer (EDL) effect is observed in microporous SiO{sub 2} dielectric films deposited at room temperature by plasma-enhanced chemical vapor deposition method. Indium tin oxide thin-film transistors gated by such microporous SiO{sub 2} gate dielectric are fabricated at room temperature, and a low operating voltage of 1.5 V is obtained due to the huge EDL specific capacitance (2.14 {mu}F/cm{sup 2}). The field-effect electron mobility is estimated to be 118 cm{sup 2} V{sup -1} s{sup -1}. Current on/off ratio and subthreshold gate voltage swing are estimated to be 5x10{sup 6} and 92 mV/decade, respectively. Room-temperature deposited microporous SiO{sub 2} dielectric is promising for low-power field-effect transistors on temperature sensitive substrates.

• OSTI ID: 21294491
• Journal Information: Applied Physics Letters, Journal Name: Applied Physics Letters Journal Issue: 22 Vol. 95; ISSN APPLAB; ISSN 0003-6951
• Country of Publication: United States
• Language: English

Related Subjects

36 MATERIALS SCIENCE
CAPACITANCE
CHEMICAL VAPOR DEPOSITION
DIELECTRIC MATERIALS
ELECTRIC POTENTIAL
ELECTROCHEMISTRY
ELECTRON MOBILITY
FIELD EFFECT TRANSISTORS
INDIUM OXIDES
LAYERS
PLASMA
POROUS MATERIALS
SEMICONDUCTOR MATERIALS
SILICON OXIDES
SUBSTRATES
TEMPERATURE RANGE 0273-0400 K
THIN FILMS
TIN OXIDES