Structural and electrical characteristics of thin erbium oxide gate dielectrics

Journal Article · Mon Nov 27 00:00:00 EST 2006 · Applied Physics Letters

DOI:https://doi.org/10.1063/1.2399938· OSTI ID:20880111

Pan, T -M; Chen, C -L; Yeh, W W; Hou, S -J ^[1]

---

1. Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China)

A high-k erbium oxide thin film was grown on silicon substrate by reactive rf sputtering. It is found that the capacitance value of Er{sub 2}O{sub 3} gate dielectric with TaN metal gate annealed at 700 deg. C is higher compared to other annealing temperature and exhibits a lower hysteresis voltage as well as interface trap density in C-V curves. They also show negligible charge trapping under high constant voltage stress. This phenomenon is attributed to a rather well-crystallized Er{sub 2}O{sub 3} and the decrease of the interfacial layer and Er silicate thickness observed by x-ray diffraction and x-ray photoelectron spectroscopy, respectively.

• OSTI ID: 20880111
• Journal Information: Applied Physics Letters, Vol. 89, Issue 22; Other Information: DOI: 10.1063/1.2399938; (c) 2006 American Institute of Physics; Country of input: International Atomic Energy Agency (IAEA); ISSN 0003-6951
• Country of Publication: United States
• Language: English

Related Subjects

36 MATERIALS SCIENCE
ANNEALING
CAPACITANCE
DIELECTRIC MATERIALS
ELECTRIC POTENTIAL
ERBIUM OXIDES
HYSTERESIS
LAYERS
SILICATES
SILICON
SPUTTERING
STRESSES
SUBSTRATES
SURFACE COATING
TANTALUM NITRIDES
THICKNESS
THIN FILMS
TRAPPING
X-RAY DIFFRACTION
X-RAY PHOTOELECTRON SPECTROSCOPY