Examination of Critical Length Effect in Copper Interconnects With Oxide and Low-k Dielectrics
- CMOS Platform Device Development, Technology Solutions Organization, Freescale Semiconductor, Inc., Austin, TX 78721 (United States)
- Advanced Products Research and Development Laboratory, Technology Solutions Organization, Freescale Semiconductor, Inc., Austin, TX 78721 (United States)
As technology moves toward faster microelectronic devices with smaller feature sizes, copper is replacing aluminum-copper alloy and low-k dielectric is replacing oxide as the materials of choice for advanced interconnect integrations. Copper not only brings to the table the advantage of lower resistivity, but also exhibits better electromigration performance when compared to Al(Cu). Low-k dielectric materials are advantageous because they reduce power consumption and improve signal delay. Due to these advantages, the industry trend is moving towards integrating copper and low-k dielectric for high performance interconnects. The purpose of this study is to evaluate the critical length effect in single-inlaid copper interconnects and determine the critical product (jl)c, for a variety of integrations, examining the effect of ILD (oxide vs. low-k), geometry, and stress temperature.
- OSTI ID:
- 20630471
- Journal Information:
- AIP Conference Proceedings, Vol. 741, Issue 1; Conference: 7. international workshop on stress-induced phenomena in metallization, Austin, TX (United States), 14-16 Jun 2004; Other Information: DOI: 10.1063/1.1845846; (c) 2004 American Institute of Physics; Country of input: International Atomic Energy Agency (IAEA); ISSN 0094-243X
- Country of Publication:
- United States
- Language:
- English
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