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Title: Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors

Abstract

The authors present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO{sub 2}/Si interface. They have achieved a significant lifetime improvement (90 {times}) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization.

Authors:
; ; ; ; ; ; ; ;
Publication Date:
Research Org.:
Univ. of Illinois, Urbana, IL (US)
Sponsoring Org.:
US Department of Energy
OSTI Identifier:
20067760
Alternate Identifier(s):
OSTI ID: 20067760
Resource Type:
Journal Article
Journal Name:
IEEE Electron Device Letters (Institute of Electrical and Electronics Engineers)
Additional Journal Information:
Journal Volume: 21; Journal Issue: 5; Other Information: PBD: May 2000; Journal ID: ISSN 0741-3106
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; MOS TRANSISTORS; ANNEALING; DEUTERIUM; CHARGE CARRIERS; RELIABILITY; CARRIER LIFETIME

Citation Formats

Lee, J., Cheng, K., Chen, Z., Hess, K., Lyding, J.W., Kim, Y.K., Lee, H.S., Kim, Y.W., and Suh, K.P. Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors. United States: N. p., 2000. Web.
Lee, J., Cheng, K., Chen, Z., Hess, K., Lyding, J.W., Kim, Y.K., Lee, H.S., Kim, Y.W., & Suh, K.P. Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors. United States.
Lee, J., Cheng, K., Chen, Z., Hess, K., Lyding, J.W., Kim, Y.K., Lee, H.S., Kim, Y.W., and Suh, K.P. Mon . "Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors". United States.
@article{osti_20067760,
title = {Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors},
author = {Lee, J. and Cheng, K. and Chen, Z. and Hess, K. and Lyding, J.W. and Kim, Y.K. and Lee, H.S. and Kim, Y.W. and Suh, K.P.},
abstractNote = {The authors present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO{sub 2}/Si interface. They have achieved a significant lifetime improvement (90 {times}) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization.},
doi = {},
journal = {IEEE Electron Device Letters (Institute of Electrical and Electronics Engineers)},
issn = {0741-3106},
number = 5,
volume = 21,
place = {United States},
year = {2000},
month = {5}
}