DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Song, Shihao; Chong, Harry; Balaji, Adarsha; Das, Anup; Shackleford, James; Kandasamy, Nagarajan

doi:10.1145/3479156

Title: DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Journal Article · Sat May 28 00:00:00 EDT 2022 · ACM Transactions on Embedded Computing Systems

DOI:https://doi.org/10.1145/3479156· OSTI ID:1980837

Song, Shihao ^[1]; Chong, Harry ^[1]; Balaji, Adarsha ^[1];

^[1]; Shackleford, James ^[1]; Kandasamy, Nagarajan ^[1]

Drexel University, Philadelphia, PA, USA

Spiking Neural Networks (SNNs) are an emerging computation model that uses event-driven activation and bio-inspired learning algorithms. SNN-based machine learning programs are typically executed on tile-based neuromorphic hardware platforms, where each tile consists of a computation unit called a crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware performance, e.g., throughput. We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware. The proposed framework works in four steps. First, it analyzes a machine learning program and generates SNN workload using representative data. Second, it partitions the SNN workload and generates clusters that fit on crossbars of the target neuromorphic hardware. Third, it exploits the rich semantics of the Synchronous Dataflow Graph (SDFG) to represent a clustered SNN program, allowing for performance analysis in terms of key hardware constraints such as number of crossbars, dimension of each crossbar, buffer space on tiles, and tile communication bandwidth. Finally, it uses a novel scheduling algorithm to execute clusters on crossbars of the hardware, guaranteeing hardware performance. We evaluate DFSynthesizer with 10 commonly used machine learning programs. Our results demonstrate that DFSynthesizer provides a much tighter performance guarantee compared to current mapping approaches.

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Research Organization:: Drexel Univ., Philadelphia, PA (United States)

Sponsoring Organization:: USDOE Office of Science (SC)

DOE Contract Number:: SC0022014

OSTI ID:: 1980837

Journal Information:: ACM Transactions on Embedded Computing Systems, Vol. 21, Issue 3; ISSN 1539-9087

Publisher:: Association for Computing Machinery (ACM)

Country of Publication:: United States

Language:: English

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