Purdue University School of Materials Engineering Neil Armstrong Hall of Engineering 701 West Stadium Avenue West Lafayette IN 47907‐2045 USA
University of Cambridge Department of Materials Science &, Metallurgy 27 Charles Babbage Road Cambridge CB3 0FS UK
Purdue University Elmore Family School of Electrical and Computer Engineering Neil Armstrong Hall of Engineering 701 West Stadium Avenue West Lafayette IN 47907‐2045 USA
Center for Integrated Nanotechnologies (CINT) Los Alamos National Laboratory Los Alamos NM 87545 USA
University at Buffalo, the State University of New York School of Engineering and Applied Sciences Department of Materials Design and Innovation 136 Bell Hall Buffalo NY 14260 USA
Purdue University School of Materials Engineering Elmore Family School of Electrical and Computer Engineering Neil Armstrong Hall of Engineering 701 West Stadium Avenue, Room 2235 West Lafayette IN 47907‐2045 USA
Defect engineering in valence change memories aimed at tuning the concentration and transport of oxygen vacancies are studied extensively, however mostly focusing on contribution from individual extended defects such as single dislocations and grain boundaries. In this work, the impact of engineering large numbers of grain boundaries on resistive switching mechanisms and performances is investigated. Three different grain morphologies, that is, “random network,” “columnar scaffold,” and “island‐like,” are realized in CeO 2 thin films. The devices with the three grain morphologies demonstrate vastly different resistive switching behaviors. The best overall resistive switching performance is shown in the devices with “columnar scaffold” morphology, where the vertical grain boundaries extending through the film facilitate the generation of oxygen vacancies as well as their migration under external bias. The observation of both interfacial and filamentary switching modes only in the devices with a “columnar scaffold” morphology further confirms the contribution from grain boundaries. In contrast, the “random network” or “island‐like” structures result in excessive or insufficient oxygen vacancy concentration migration paths. The research provides design guidelines for grain boundary engineering of oxide‐based resistive switching materials to tune the resistive switching performances for memory and neuromorphic computing applications.
@article{osti_1960671,
author = {Dou, Hongyi and Hellenbrand, Markus and Xiao, Ming and Hu, Zedong and Kunwar, Sundar and Chen, Aiping and MacManus‐Driscoll, Judith L. and Jia, Quanxi and Wang, Haiyan},
title = {Engineering of Grain Boundaries in CeO <sub>2</sub> Enabling Tailorable Resistive Switching Properties},
annote = {Abstract Defect engineering in valence change memories aimed at tuning the concentration and transport of oxygen vacancies are studied extensively, however mostly focusing on contribution from individual extended defects such as single dislocations and grain boundaries. In this work, the impact of engineering large numbers of grain boundaries on resistive switching mechanisms and performances is investigated. Three different grain morphologies, that is, “random network,” “columnar scaffold,” and “island‐like,” are realized in CeO 2 thin films. The devices with the three grain morphologies demonstrate vastly different resistive switching behaviors. The best overall resistive switching performance is shown in the devices with “columnar scaffold” morphology, where the vertical grain boundaries extending through the film facilitate the generation of oxygen vacancies as well as their migration under external bias. The observation of both interfacial and filamentary switching modes only in the devices with a “columnar scaffold” morphology further confirms the contribution from grain boundaries. In contrast, the “random network” or “island‐like” structures result in excessive or insufficient oxygen vacancy concentration migration paths. The research provides design guidelines for grain boundary engineering of oxide‐based resistive switching materials to tune the resistive switching performances for memory and neuromorphic computing applications. },
doi = {10.1002/aelm.202201186},
url = {https://www.osti.gov/biblio/1960671},
journal = {Advanced Electronic Materials},
issn = {ISSN 2199-160X},
number = {5},
volume = {9},
place = {United States},
publisher = {Wiley Blackwell (John Wiley & Sons)},
year = {2023},
month = {03}}