NISQ+: Boosting quantum computing power by approximating quantum error correction

Holmes, Adam; Jokar, Mohammad Reza; Pasandi, Ghasem; Ding, Yongshan; Pedram, Massoud; Chong, Frederic T.

doi:10.1109/isca45697.2020.00053

NISQ+: Boosting quantum computing power by approximating quantum error correction

Journal Article · Fri May 01 00:00:00 EDT 2020 · Proceedings - International Symposium on Computer Architecture (ICSA)

DOI:https://doi.org/10.1109/isca45697.2020.00053· OSTI ID:1865600

Holmes, Adam ^[1]; Jokar, Mohammad Reza ^[2]; Pasandi, Ghasem ^[3]; Ding, Yongshan ^[2]; Pedram, Massoud ^[3]; Chong, Frederic T. ^[2]

Univ. of Chicago, IL (United States); Intel Corporation, Seattle, OR (United States); The University of Chicago
Univ. of Chicago, IL (United States)
Univ. of California, Los Angeles, CA (United States)

Quantum computers are growing in size, and design decisions are being made now that attempt to squeeze more computation out of these machines. In this spirit, we design a method to boost the computational power of near-term quantum computers by adapting protocols used in quantum error correction to implement "Approximate Quantum Error Correction (AQEC)." By approximating fully-fledged error correction mechanisms, we can increase the compute volume (qubits × gates, or "Simple Quantum Volume (SQV)") of near-term machines. The crux of our design is a fast hardware decoder that can approximately decode detected error syndromes rapidly. Specifically, we demonstrate a proof-of-concept that approximate error decoding can be accomplished online in near-term quantum systems by designing and implementing a novel algorithm in Single-Flux Quantum (SFQ) superconducting logic technology. This avoids a critical decoding backlog, hidden in all offline decoding schemes, that leads to idle time exponential in the number of T gates in a program. Our design utilizes one SFQ processing module per physical qubit. Employing state-of-the-art SFQ synthesis tools, we show that the circuit area, power, and latency are within the constraints of contemporary quantum system designs. Under pure dephasing error models, the proposed accelerator and AQEC solution is able to expand SQV by factors between 3,402 and 11,163 on expected near-term machines. The decoder achieves a 5% accuracy-threshold and pseudo-thresholds of ~ 5%,4.75%,4.5%, and 3.5% physical error-rates for code distances 3,5,7, and 9. Decoding solutions are achieved in a maximum of ~20 nanoseconds on the largest code distances studied. By avoiding the exponential idle time in offline decoders, we achieve a 10x reduction in required code distances to achieve the same logical performance as alternative designs.

View Accepted Manuscript (DOE)

Research Organization:: Univ. of Chicago, IL (United States)

Sponsoring Organization:: USDOE Office of Science (SC), Engineering & Technology; National Science Foundation (NSF)

Grant/Contract Number:: SC0020331; SC0020289

OSTI ID:: 1865600

Journal Information:: Proceedings - International Symposium on Computer Architecture (ICSA), Journal Name: Proceedings - International Symposium on Computer Architecture (ICSA) Vol. 2020; ISSN 1063-6897

Publisher:: IEEECopyright Statement

Country of Publication:: United States

Language:: English

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