A High-Efficiency Isolated PFC AC-DC Topology with Reduced Number of Semiconductor Devices
Journal Article
·
· IEEE Journal of Emerging and Selected Topics in Power Electronics
- Prince Sattam Bin Abdulaziz Univ., Wadi Addawaser (Saudi Arabia)
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Univ. Nacional de Rio Cuarto (UNRC), Río Cuarto, Córdoba (Argentina). Consejo Nacional de Investigaciones Científicas y Técnicas (CONICET), and Inst. de Investigaciones en Tecnologıas Energeticas y Materiales Avanzados (IITEMA)
- Univ. of Arkansas, Fayetteville, AR (United States)
A new three-level isolated ac-dc power factor correction (PFC) topology with a minimum number of semiconductor devices is the focus of this paper. This topology provides a high input power factor (PF), soft-switching, and higher efficiency than existing isolated ac-dc converters. Furthermore, the proposed circuit has lower voltage rating requirements for the secondary side devices, which leads to a lower total cost and minimizes total converter losses. This article presents a theoretical analysis describing the complete characterization of this new topology, and experimental results on a 1-kW prototype showing high PF and efficiency throughout the operating range.
- Research Organization:
- Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Organization:
- USDOE Office of Electricity (OE); USDOE National Nuclear Security Administration (NNSA)
- Grant/Contract Number:
- AC04-94AL85000; NA0003525
- OSTI ID:
- 1769930
- Report Number(s):
- SAND--2021-1947J; 694125
- Journal Information:
- IEEE Journal of Emerging and Selected Topics in Power Electronics, Journal Name: IEEE Journal of Emerging and Selected Topics in Power Electronics Journal Issue: 4 Vol. 10; ISSN 2168-6777
- Publisher:
- IEEECopyright Statement
- Country of Publication:
- United States
- Language:
- English
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