Performance Assessment of Emerging Memories Through FPGA Emulation

Journal Article · Thu Nov 08 00:00:00 EST 2018 · IEEE Micro

DOI:https://doi.org/10.1109/mm.2018.2877291· OSTI ID:1734593

Jain, Abhishek Kumar ^[1]; Lloyd, Scott ^[1]; Gokhale, Maya ^[1]

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1. Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Emerging memory technologies offer the prospect of large capacity, high bandwidth, and a range of access latencies ranging from DRAM-like to SSD-like. In this paper, we evaluate the performance of parallel applications on CPUs whose main memories sweep a wide range of latencies within a bandwidth cap. We use an FPGA emulator, the logic in memory emulator (LiME) to accelerate evaluation. The LiME framework uses a multiprocessor system on chip (MPSoC) combining multicore CPU, integrated memory controller, and FPGA fabric, and enables emulation orders of magnitude faster than software simulation. This work highlights the performance impact of higher latency on concurrent applications and identifies conditions under which future high latency memories can effectively be used as main memory.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE National Nuclear Security Administration (NNSA)
• Grant/Contract Number: AC52-07NA27344
• OSTI ID: 1734593
• Report Number(s): LLNL-JRNL--754877; 941579
• Journal Information: IEEE Micro, Journal Name: IEEE Micro Journal Issue: 1 Vol. 39; ISSN 0272-1732
• Publisher: IEEE
• Country of Publication: United States
• Language: English

Related Subjects

97 MATHEMATICS AND COMPUTING
computer science