ZFP Hardware Implementation

Technical Report · Wed Jun 17 04:00:00 EDT 2020

DOI:https://doi.org/10.2172/1642491· OSTI ID:1642491

Lloyd, G. Scott ^[1]; Lindstrom, Peter G. ^[1]

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1. Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

As core counts increase in new HPC systems with comparatively little increase in memory bandwidth, the trend is an effective decrease in memory bandwidth per core. Other bandwidth limitations in HPC systems exist between CPU and GPU memory, between system nodes, and between node memory and storage. Compression of floating-point data has the potential to reduce data movement and pressure across these communication channels. Furthermore, it has the potential to reduce the footprint of floating-point arrays stored in memory. ZFP, implemented in software, is gaining traction as an effective method in floating-point compression; however, performance gains are limited to the spare compute cycles available before reaching the bandwidth limitations of the communication channel. A hardware implementation of ZFP has the potential to raise the bar on performance. From the inception of ZFP, it was designed to accommodate a hardware implementation.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE National Nuclear Security Administration (NNSA)
• DOE Contract Number: AC52-07NA27344
• OSTI ID: 1642491
• Report Number(s): LLNL-TR--811940; 1018807
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
97 MATHEMATICS AND COMPUTING