Gate Quantum Capacitance Effects in Nanoscale Transistors

Desai, Sujay B.; Fahad, Hossain M.; Lundberg, Theodor; Pitner, Gregory; Kim, Hyungjin; Chrzan, Daryl; Wong, H.-S. Philip; Javey, Ali

doi:10.1021/acs.nanolett.9b02660

Gate Quantum Capacitance Effects in Nanoscale Transistors

Journal Article · Wed Sep 18 00:00:00 EDT 2019 · Nano Letters

DOI:https://doi.org/10.1021/acs.nanolett.9b02660· OSTI ID:1638995

^[1]; ^[1]; Lundberg, Theodor ^[2]; ^[3]; Kim, Hyungjin ^[1]; Chrzan, Daryl ^[4]; Wong, H.-S. Philip ^[3]; ^[1]

Univ. of California, Berkeley, CA (United States). Dept. of Electrical Engineering and Computer Sciences and Berkeley Sensor and Actuator Center; Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States). Materials Sciences Division
Univ. of California, Berkeley, CA (United States). Dept. of Electrical Engineering and Computer Sciences
Stanford Univ., CA (United States). Electrical Engineering
Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States). Materials Sciences Division; Univ. of California, Berkeley, CA (United States). Dept. of Materials Science and Engineering

As the physical dimensions of a transistor gate continue to shrink to a few atoms, performance can be increasingly determined by the limited electronic density of states (DOS) in the gate and the gate quantum capacitance (C_Q). We demonstrate the impact of gate C_Q and the dimensionality of the gate electrode on the performance of nanoscale transistors through analytical electrostatics modeling. For low-dimensional gates, the gate charge can limit the channel charge, and the transfer characteristics of the device become dependent on the gate DOS. Here, we experimentally observe for the first time, room-temperature gate quantization features in the transfer characteristics of single-walled carbon nanotube (CNT)-gated ultrathin silicon-on-insulator (SOI) channel transistors; features which can be attributed to the Van Hove singularities in the one-dimensional DOS of the CNT gate. In addition to being an important aspect of future transistor design, potential applications of this phenomenon include multilevel transistors with suitable transfer characteristics obtained via engineered gate DOS.

View Accepted Manuscript (DOE)

Research Organization:: Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)

Sponsoring Organization:: USDOE Office of Science (SC), Basic Energy Sciences (BES). Materials Sciences & Engineering Division

Grant/Contract Number:: AC02-05CH11231

OSTI ID:: 1638995

Journal Information:: Nano Letters, Journal Name: Nano Letters Journal Issue: 10 Vol. 19; ISSN 1530-6984

Publisher:: American Chemical SocietyCopyright Statement

Country of Publication:: United States

Language:: English

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