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Title: Method and apparatus for power delivery to a die stack via a heat spreader

Patent ·
OSTI ID:1632416

Various chip stack power delivery circuits are disclosed. In one aspect, an apparatus is provided that includes a stack of semiconductor chips that has an uppermost semiconductor chip and a lowermost semiconductor chip. A heat spreader is positioned on the uppermost semiconductor chip. A power transfer circuit is configured to transfer electric power from the heat spreader to the uppermost semiconductor chip.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344; B620717
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
10,529,677
Application Number:
15/965,425
OSTI ID:
1632416
Resource Relation:
Patent File Date: 04/27/2018
Country of Publication:
United States
Language:
English

References (7)

Power Distribution and Thermal Solution for Direct Stacked Integrated Circuits patent-application August 2014
Heat Sink patent-application October 2014
Power Delivery to Three-Dimensional Chips patent-application June 2015
Methods for assembling multiple semiconductor devices patent April 2007
Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same patent-application September 2017
Die Stacking with Coupled Electrical Interconnects to Align Proximity Interconnects patent-application October 2013
Stacked-Chip Device patent-application March 2010

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