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The ETROC Project: Precision Timing ASIC Development for LGAD-based CMS Endcap Timing Layer (ETL) Upgrade

Technical Report ·
DOI:https://doi.org/10.2172/1623361· OSTI ID:1623361
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  1. Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
  2. Southern Methodist Univ., Dallas, TX (United States)
  3. Northwestern Univ., Evanston, IL (United States)
  4. Kyungpook National Univ., Daegu (Korea, Republic of)
+ Show Author Affiliations
The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD silicon devices to be read out by ETROCs for precision timing measurement with down to 30 ps timing resolution. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel cell being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. Approximately 15% of the sensors near the highest eta region will experience hadron fluence above 1e15 neq/cm² towards end of operation of HL-LHC, resulting in small signal amplitude with LGAD gain reduced to around 10. For this reason, the front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile.
Research Organization:
Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
Sponsoring Organization:
USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
DOE Contract Number:
AC02-07CH11359
OSTI ID:
1623361
Report Number(s):
FERMILAB-POSTER--19-119-E; oai:inspirehep.net:1796314
Country of Publication:
United States
Language:
English

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97 MATHEMATICS AND COMPUTING