Design of a Single Controller for Multiple Paralleled Inverters

Conference · Fri Mar 01 04:00:00 EST 2019 · Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition (APEC)

DOI:https://doi.org/10.1109/APEC.2019.8721768· OSTI ID:1560417

Niu, Jiahao ^[1]; Chen, Ruirui ^[1]; Zhang, Zheyu ^[1]; Gui, Handong ^[1]; Wang, Fei ^[2]; Tolbert, Leon ^[2]; Blalock, Benjamin J. ^[2]; Costinett, Daniel ^[2]; Choi, Benjamin ^[3]

---

1. The University of Tennessee, Knoxville
2. ORNL
3. NASA Glenn Research Center, Cleveland

Paralleling power electronics inverters is an effective way to increase dc-ac system power level. Accurately synchronized switching action and independent closed-loop regulator are necessary to prevent circulating current in paralleled inverters. There are many challenges for the controller design, when the number of paralleled inverters is large, and control period gets short for high switching frequency applications. This paper presents a single controller design based on DSP + FPGA that is suitable for paralleling multiple inverters. A simple synchronization scheme between DSP and FPGA based on universal parallel port (UPP) is proposed to eliminate the synchronization delay among inverters, and independent control of each converter can also be implemented. The controller is built for a system consisting of 4 paralleled three-level, three-phase high frequency ANPC inverters using space vector modulation, and it can be easily adopted to other topologies and modulations. Experimental results have demonstrated the effectiveness of this controller.

• Research Organization: Oak Ridge National Laboratory (ORNL), Oak Ridge, TN (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC05-00OR22725
• OSTI ID: 1560417
• Conference Information: Journal Name: Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition (APEC) Journal Volume: 2019
• Country of Publication: United States
• Language: English