High memory capacity DRAM SIMM
|
patent
|
December 1993 |
Fault-tolerant computer system with hidden local memory refresh
|
patent
|
December 1995 |
Method and apparatus for high density sixteen and thirty-two megabyte single in-line memory module
|
patent
|
April 1996 |
Cache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memory
|
patent
|
September 1996 |
Source-clock-synchronized memory system and memory unit
|
patent
|
March 2000 |
Method and apparatus for utilizing parallel memory in a serial memory system
|
patent
|
April 2001 |
Apparatus and method for topography dependent signaling
|
patent
|
November 2001 |
Means and method for a synchronous network communications system
|
patent
|
April 2002 |
Memory system for synchronized and high speed data transfer
|
patent
|
November 2002 |
Memory system including a point-to-point linked memory subsystem
|
patent
|
December 2002 |
Predictive thermal control used with a vacuum enclosed coil assembly of a magnetic resonance imaging device
|
patent
|
February 2003 |
Computer system providing low skew clock signals to a synchronous memory unit
|
patent
|
October 2003 |
Apparatus and method for controlling a master/slave system via master device synchronization
|
patent
|
January 2005 |
Method of matching different signal propagation times between a controller and at least two processing units, and a computer system
|
patent
|
October 2005 |
Memory control chip, control method and control circuit
|
patent
|
February 2006 |
Memory channel with unidirectional links
|
patent
|
January 2007 |
Instruction memory hierarchy for an embedded processor
|
patent
|
April 2007 |
System and method for improving performance in computer memory systems supporting multiple memory access latencies
|
patent
|
May 2007 |
Memory system and device with serialized data transfer
|
patent
|
December 2007 |
System including a host connected to a plurality of memory modules via a serial memory interconnect
|
patent
|
September 2008 |
Apparatus and Method to Improve Performance of Reads from and Writes to Shared Memory Locations
|
patent-application
|
March 2002 |
Memory controller for supporting a plurality of different memory accesse modes
|
patent-application
|
April 2003 |
Memory system
|
patent-application
|
October 2003 |
Memory system and control method for the same
|
patent-application
|
December 2003 |
Transferring data in selectable transfer modes
|
patent-application
|
May 2004 |
System including a host connected to a plurality of memory modules via a serial memory interconnet
|
patent-application
|
November 2004 |
Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)
|
patent-application
|
November 2004 |
System including a host connected serially in a chain to one or more memory modules that include a cache
|
patent-application
|
July 2005 |
Generic method and apparatus for implementing source synchronous interface in platform ASIC
|
patent-application
|
October 2005 |
Communication channel calibration using feedback
|
patent-application
|
December 2005 |
Methods and transmitters for loop-back adaptive pre-emphasis data transmission
|
patent-application
|
February 2006 |
Memory module and memory system
|
patent-application
|
February 2007 |
High speed transceiver with low power consumption
|
patent-application
|
May 2007 |
Memory Interface to Bridge Memory Buses
|
patent-application
|
May 2007 |
Memory Interface to Bridge Memory Buses
|
patent-application
|
July 2007 |
Memory system including a high-speed serial buffer
|
patent-application
|
May 2008 |
Microprocessor systems
|
patent-application
|
August 2009 |