Memory System Design for Ultra Low Power Computationally Error Resilient Processor Microarchitectures.

Conference · 01 November 2017

DOI:https://doi.org/10.1109/HPCA.2018.00065· OSTI ID:1483201

Srikanth, Sriseshan ^[1]; Rabbat, Paul ^[2]; Hein, Eric ^[1]; Deng, Bobin ^[1]; Conte, Thomas ^[1]; Debenedictis, Erik; Cook, Jeanine; Frank, Michael P

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1. Ga Tech
2. Intel

Abstract not provided.

• Research Organization: Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
• Sponsoring Organization: USDOE National Nuclear Security Administration (NNSA)
• DOE Contract Number: AC04-94AL85000
• OSTI ID: 1483201
• Report Number(s): SAND2017-12733C; 658986
• Country of Publication: United States
• Language: English