Piecewise empirical model (PEM) of resistive memory for pulsed analog and neuromorphic applications

Niroula, John; Agarwal, Sapan; Jacobs-Gedrim, Robin; Schiek, Richard L.; Hughart, David; Hsia, Alex; James, Conrad D.; Marinella, Matthew J.

doi:10.1007/s10825-017-1107-3

Piecewise empirical model (PEM) of resistive memory for pulsed analog and neuromorphic applications

Journal Article · Fri Dec 01 23:00:00 EST 2017 · Journal of Computational Electronics

DOI:https://doi.org/10.1007/s10825-017-1107-3· OSTI ID:1469639

Niroula, John ^[1]; Agarwal, Sapan ^[2]; Jacobs-Gedrim, Robin ^[1]; Schiek, Richard L. ^[1]; Hughart, David ^[1]; Hsia, Alex ^[1]; James, Conrad D. ^[1]; Marinella, Matthew J. ^[1]

Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Sandia National Laboratories (SNL-CA), Livermore, CA (United States)

With the end of Dennard scaling and the ever-increasing need for more efficient, faster computation, resistive switching devices (ReRAM), often referred to as memristors, are a promising candidate for next generation computer hardware. These devices show particular promise for use in an analog neuromorphic computing accelerator as they can be tuned to multiple states and be updated like the weights in neuromorphic algorithms. Modeling a ReRAM-based neuromorphic computing accelerator requires a compact model capable of correctly simulating the small weight update behavior associated with neuromorphic training. These small updates have a nonlinear dependence on the initial state, which has a significant impact on neural network training. Consequently, we propose an empirically derived general purpose model that can accurately capture the nonlinearity of an arbitrary two-terminal device to match pulse measurements important for neuromorphic computing applications. By defining the state of the device to be proportional to its current, the model parameters can be extracted from a series of voltages pulses that mimic the behavior of a device in an analog neuromorphic computing accelerator. This allows for a general, accurate, and intuitive compact circuit model that is applicable to different resistance switching device technologies. In this work we explain the details of the model, implement the model in the circuit simulator Xyce, and give an example of its usage to model a specific Ta/TaO_x device.

View Accepted Manuscript (DOE)

Research Organization:: Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Sponsoring Organization:: USDOE National Nuclear Security Administration (NNSA)

Grant/Contract Number:: AC04-94AL85000

OSTI ID:: 1469639

Report Number(s):: SAND2018--9642J; PII: 1107

Journal Information:: Journal of Computational Electronics, Journal Name: Journal of Computational Electronics Journal Issue: 4 Vol. 16; ISSN 1569-8025

Publisher:: SpringerCopyright Statement

Country of Publication:: United States

Language:: English

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