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Title: Compensating for parasitic voltage drops in circuit arrays

Patent ·
OSTI ID:1469143
;

Various technologies for improving uniformity of operation of elements in an array circuit are described herein. In an exemplary embodiment, a plurality of resistive elements are incorporated into an array circuit such that voltages developed across any two elements is substantially the same when an equal voltage is applied to energize the elements. In a crossbar array circuit that comprises a plurality of elements arranged in rows and columns, the resistance of each of the resistive elements is based upon a row or column to which the resistive element is connected.

Research Organization:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
NA0003525
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
Patent Number(s):
10,043,855
Application Number:
15/841,670
OSTI ID:
1469143
Resource Relation:
Patent File Date: 2017 Dec 14
Country of Publication:
United States
Language:
English

References (9)

High density resistor array patent October 1988
Balanced and bi-directional bit line paths for memory arrays with programmable memory cells patent March 2009
Display apparatus, and image signal processing apparatus and drive control apparatus for the same patent-application July 2003
Driving apparatus, driver circuit, and image display apparatus patent-application January 2004
Drive circuit patent-application November 2004
Resistance balance circuit patent-application September 2008
Rechargeable Battery Array patent-application March 2009
Memory Device with Asymmetrical Bit Cell Arrays and Balanced Resistance and Capacitance patent-application May 2012
Display Device patent-application June 2013

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