Mask substrate requirements and development for extreme ultraviolet lithography (EUVL)
The mask is deemed one of the areas that require significant research and development in EUVL. Silicon wafers will be used for mask substrates for an alpha-class EUVL exposure tool due to their low-defect levels and high quality surface finish. However, silicon has a large coefficient of thermal expansion that leads to unacceptable image distortion due to absorption of EUV light. A low thermal expansion glass or glass-ceramic is likely to be required in order to meet error budgets for the 70nm node and beyond. Since EUVL masks are used in reflection, they are coated with multilayers prior to patterning. Surface imperfections, such as polishing marks, particles, scratches, or digs, are potential nucleation sites for defects in the multilayer coating, which could result in the printed defects. Therefore we are accelerating developments in the defect reduction and surface finishing of low thermal expansion mask substrates in order to understand long-term issues in controlling printable defects, and to establish the infrastructure for supplying masks. In this paper, we explain the technical requirements for EUVL mask substrates and describe our efforts in establishing a SEMI standard for EUVL masks. We will also report on the early progress of our suppliers in producing low thermal-expansion mask substrates for our development activities.
- Research Organization:
- Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE Office of Defense Programs (DP) (US)
- DOE Contract Number:
- W-7405-ENG-48
- OSTI ID:
- 14670
- Report Number(s):
- UCRL-JC-135884; TRN: AH200129%%377
- Resource Relation:
- Conference: 19th Annual Bay Area Chrom Users Society Symposium on Photomask Technology and Management, Monterey, CA (US), 09/15/1999--09/17/1999; Other Information: PBD: 28 Sep 1999
- Country of Publication:
- United States
- Language:
- English
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