Photonic Memory Controller Module (P-MCM)
- Analog Photonics LLC
The Department of Energy has a persistent and strong need for high performance super computers to be used in applications spanning from climate change to nuclear process simulations. However, as the computational speed required by the cloud computing and high-performance computing continues to scale up, the required memory bandwidth is not keeping pace. This is one of the many issues referred to as the “Memory Wall.” Conventional electronic interconnects are simply not able to tackle this problem due to the inherent power consumption challenges of communicating high data rate links over distances beyond the chip scale. The lacking bandwidth-density, limited pin-counts, and distance-dependent power dissipation severely limit the performance of electronic interconnected systems. In this Program, a team of industry and academic experts in optical interconnect design have come together to develop optical components and network architectures for the next generation high-bandwidth memory modules for DOE relevant high-performance computing applications. The main outcomes and achievements from the Phase I effort include: Task 1. Columbia University investigated possible architectures to achieve the aforementioned technical objectives. Subsystem components that are developed by the members of the project are integrated into the OCM testbed to allow system evaluation of cost, performance and power. Task 2. Freedom Photonics designed and deployed the tunable laser modules to Columbia University/PLC Connections for WDM system integration and packaging testing. O-band tunable laser design is developed for Phase II at low-power and ns-wavelength switching operating in uncooled mechanism at 15-55°C ambient temperature range. Task 3. Analog Photonics assisted in the design and characterization of the optical switch fabric for the OCM testbed. Packaging requirements were delivered to PLCC for high-count and low-loss fiber attachment. SiP transceiver modules were fabricated and evaluated for power efficient WDM links. Task 4. Columbia University developed DDR3 memory controller for optical WDM links for pahse-1 testbed, and Hybrid-Memory-Cube (HMC) controller for phase-2 system evaluation. The FPGA memory controller module interfaces with the memory and manages the data read and write operations. The control plane for the photonic switch fabric was also developed and works in conjunction with the memory controller module Task 5. PLC Connections deployed a packaged silicon photonic switch with an array of 18 fibers attached at low optical loss. Dense packaging proof-of-concept was experimented and shown to be scalable for smaller fiber pitch capability. A mechanism for attaching Freedom’s tunable laser modules was developed. Task 6. Columbia University integrated the subcomponents in the OCM testbed to evaluate complete performance of the system. Freedom Photonics’ tunable lasers were used as the foundation for the CPU-memory optical interface. The silicon photonic chip, designed by Analog Photonics and packaged by PLCC, was deployed in the OCM system. The FPGA based testbed was designed to fit HMC modules and new SiP architectures for phase-2.
- Research Organization:
- Analog Photonics
- Sponsoring Organization:
- USDOE Office of Science (SC)
- DOE Contract Number:
- SC0017182
- OSTI ID:
- 1411065
- Type / Phase:
- SBIR (Phase I)
- Report Number(s):
- DOE-AP-SBIR-2222; 079091194
- Country of Publication:
- United States
- Language:
- English
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