Sparse Matrix-Vector Multiplication on Multicore and Accelerators

Book · Tue Dec 07 04:00:00 EST 2010

DOI:https://doi.org/10.1201/b10376· OSTI ID:1407092

Williams, Samuel W. ^[1]; Bell, Nathan ^[2]; Choi, Jee Whan ^[3]; Garland, Michael ^[2]; Oliker, Leonid ^[1]; Vuduc, Richard ^[3]

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1. Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
2. NVIDIA Research, Santa Clara, CA (United States)
3. Georgia Inst. of Technology, Atlanta, GA (United States)

This chapter consolidates recent work on the development of high performance multicore and accelerator-based implementations of sparse matrix-vector multiplication (SpMV). As an object of study, SpMV is an interesting computation for two key reasons. First, it appears widely in applications in scientific and engineering computing, financial and economic modeling, and information retrieval, among others, and is therefore of great practical interest. Secondly, it is both simple to describe but challenging to implement well, since its performance is limited by a variety of factors, including low computational intensity, potentially highly irregular memory access behavior, and a strong input dependence that be known only at run time. Thus, we believe SpMV is both practically important and provides important insights for understanding the algorithmic and implementation principles necessary to making effective use of state-of-the-art systems.

• Research Organization: Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
• Sponsoring Organization: USDOE Office of Science (SC), Advanced Scientific Computing Research (ASCR) (SC-21)
• DOE Contract Number: AC02-05CH11231
• OSTI ID: 1407092
• Country of Publication: United States
• Language: English

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