skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Snowflake: A Lightweight Portable Stencil DSL

Journal Article · · Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017
 [1];  [1];  [1];  [2];  [2];  [1]
  1. Univ. of California, Berkeley, CA (United States). Dept. of Electrical Engineering and Computer Science
  2. Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States). Computational Research Division

Stencil computations are not well optimized by general-purpose production compilers and the increased use of multicore, manycore, and accelerator-based systems makes the optimization problem even more challenging. In this paper we present Snowflake, a Domain Specific Language (DSL) for stencils that uses a 'micro-compiler' approach, i.e., small, focused, domain-specific code generators. The approach is similar to that used in image processing stencils, but Snowflake handles the much more complex stencils that arise in scientific computing, including complex boundary conditions, higher-order operators (larger stencils), higher dimensions, variable coefficients, non-unit-stride iteration spaces, and multiple input or output meshes. Snowflake is embedded in the Python language, allowing it to interoperate with popular scientific tools like SciPy and iPython; it also takes advantage of built-in Python libraries for powerful dependence analysis as part of a just-in-time compiler. We demonstrate the power of the Snowflake language and the micro-compiler approach with a complex scientific benchmark, HPGMG, that exercises the generality of stencil support in Snowflake. By generating OpenMP comparable to, and OpenCL within a factor of 2x of hand-optimized HPGMG, Snowflake demonstrates that a micro-compiler can support diverse processor architectures and is performance-competitive whilst preserving a high-level Python implementation.

Research Organization:
Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
Sponsoring Organization:
USDOE Office of Science (SC), Advanced Scientific Computing Research (ASCR); Defense Advanced Research Projects Agency (DARPA)
Grant/Contract Number:
AC02-05CH11231; HR0011-12-2-0016
OSTI ID:
1379895
Journal Information:
Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017, Conference: 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Lake Buena Vista, FL (United States), 29 May-2 Jun 2017
Country of Publication:
United States
Language:
English
Citation Metrics:
Cited by: 6 works
Citation information provided by
Web of Science

Similar Records

Helium: lifting high-performance stencil kernels from stripped x86 binaries to halide DSL code
Journal Article · Wed Jun 03 00:00:00 EDT 2015 · ACM SIGPLAN Notices · OSTI ID:1379895

Using Verified Lifting to Optimize Legacy Stencil Codes (Final Project Report)
Technical Report · Wed Feb 10 00:00:00 EST 2021 · OSTI ID:1379895

Closeout Report for DE-SC0018121
Technical Report · Fri Apr 28 00:00:00 EDT 2023 · OSTI ID:1379895