A fast shaping low power amplifier-comparator integrated circuit for silicon strip detectors

Journal Article · Tue Aug 01 04:00:00 EDT 1995 · IEEE Transactions on Nuclear Science

DOI:https://doi.org/10.1109/23.467788· OSTI ID:136906

Spencer, E; Dorfan, D; Grillo, A; Kashigin, S; Rowe, W; Webster, A; Wilder, M ^[1]

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1. Univ. of California, Santa Cruz, CA (United States)

The authors have designed and tested a 64 channel amplifier-comparator integrated circuit on the Maxim SHPi bipolar process. The low power design, 840 {micro}W/channel, is intended for use as a front end with high clock rate silicon strip detector systems. Peaking time at the comparator input is 20 ns, for good double pulse resolution, and noise is near optimum for the technology used. They have used the chip successfully in a proton beam test at KEK in Japan with a 40 MHz data clock.

• OSTI ID: 136906
• Report Number(s): CONF-941061--
• Journal Information: IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 4Pt1 Vol. 42; ISSN 0018-9499; ISSN IETNAE
• Country of Publication: United States
• Language: English

Related Subjects

43 PARTICLE ACCELERATORS
44 INSTRUMENTATION
INCLUDING NUCLEAR AND PARTICLE DETECTORS
AMPLIFIERS
CERN LHC
COMPARATOR CIRCUITS
DESIGN
INTEGRATED CIRCUITS
PERFORMANCE TESTING
READOUT SYSTEMS
SI SEMICONDUCTOR DETECTORS
SUPERCONDUCTING SUPER COLLIDER