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Title: Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL

Abstract

The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. In this report, we evaluate the performance of the kernel using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board. Compared to the M506 module, the board provides more hardware resources for a larger design exploration space. The kernel performance is measured with the compute kernel throughput, an upper bound to the FPGA throughput. The reportmore » presents the experimental results in details. The Appendix lists the kernel source code.« less

Authors:
 [1];  [1];  [1];  [1]
  1. Argonne National Lab. (ANL), Argonne, IL (United States)
Publication Date:
Research Org.:
Argonne National Lab. (ANL), Argonne, IL (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1357909
Report Number(s):
ANL/ALCF-17/3
135284
DOE Contract Number:
AC02-06CH11357
Resource Type:
Technical Report
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING; OpenCL; FPGA; AES

Citation Formats

Jin, Zheming, Yoshii, Kazutomo, Finkel, Hal, and Cappello, Franck. Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL. United States: N. p., 2017. Web. doi:10.2172/1357909.
Jin, Zheming, Yoshii, Kazutomo, Finkel, Hal, & Cappello, Franck. Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL. United States. doi:10.2172/1357909.
Jin, Zheming, Yoshii, Kazutomo, Finkel, Hal, and Cappello, Franck. Thu . "Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL". United States. doi:10.2172/1357909. https://www.osti.gov/servlets/purl/1357909.
@article{osti_1357909,
title = {Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL},
author = {Jin, Zheming and Yoshii, Kazutomo and Finkel, Hal and Cappello, Franck},
abstractNote = {The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. In this report, we evaluate the performance of the kernel using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board. Compared to the M506 module, the board provides more hardware resources for a larger design exploration space. The kernel performance is measured with the compute kernel throughput, an upper bound to the FPGA throughput. The report presents the experimental results in details. The Appendix lists the kernel source code.},
doi = {10.2172/1357909},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Thu Apr 20 00:00:00 EDT 2017},
month = {Thu Apr 20 00:00:00 EDT 2017}
}

Technical Report:

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