Addressing Thermal and Performance Variability Issues in Dynamic Processors

Technical Report · Wed Mar 01 00:00:00 EST 2017

DOI:https://doi.org/10.2172/1353371· OSTI ID:1353371

Yoshii, Kazutomo ^[1]; Llopis, Pablo ^[2]; Zhang, Kaicheng ^[3]; Luo, Yingyi ^[3]; Ogrenci-Memik, Seda ^[3]; Memik, Gokhan ^[3]; Sankaran, Rajesh ^[1]; Beckman, Pete ^[1]

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1. Argonne National Lab. (ANL), Argonne, IL (United States)
2. Univ. Carlos III de Madrid (Spain)
3. Northwestern Univ., Evanston, IL (United States)

As CMOS scaling nears its end, parameter variations (process, temperature and voltage) are becoming a major concern. To overcome parameter variations and provide stability, modern processors are becoming dynamic, opportunistically adjusting voltage and frequency based on thermal and energy constraints, which negatively impacts traditional bulk-synchronous parallelism-minded hardware and software designs. As node-level architecture is growing in complexity, implementing variation control mechanisms only with hardware can be a challenging task. In this paper we investigate a software strategy to manage hardwareinduced variations, leveraging low-level monitoring/controlling mechanisms.

• Research Organization: Argonne National Lab. (ANL), Argonne, IL (United States)
• Sponsoring Organization: USDOE Office of Science (SC)
• DOE Contract Number: AC02-06CH11357
• OSTI ID: 1353371
• Report Number(s): ANl/MCS-TM-368; 134372
• Country of Publication: United States
• Language: English

Related Subjects

97 MATHEMATICS AND COMPUTING