Efficient packet forwarding using cyber-security aware policies

Ros-Giralt, Jordi

Title: Efficient packet forwarding using cyber-security aware policies

Patent · Tue Apr 04 00:00:00 EDT 2017

OSTI ID:1349673

Ros-Giralt, Jordi

For balancing load, a forwarder can selectively direct data from the forwarder to a processor according to a loading parameter. The selective direction includes forwarding the data to the processor for processing, transforming and/or forwarding the data to another node, and dropping the data. The forwarder can also adjust the loading parameter based on, at least in part, feedback received from the processor. One or more processing elements can store values associated with one or more flows into a structure without locking the structure. The stored values can be used to determine how to direct the flows, e.g., whether to process a flow or to drop it. The structure can be used within an information channel providing feedback to a processor.

View Patent

Cite

Export

Save

Research Organization:: Significs and Elements, LLC, New York, NY (United States)

Sponsoring Organization:: USDOE

DOE Contract Number:: SC0006343; SC0004400

Assignee:: Significs and Elements, LLC (New York, NY)

Patent Number(s):: 9,613,163

Application Number:: 14/939,881

OSTI ID:: 1349673

Resource Relation:: Patent File Date: 2015 Nov 12

Country of Publication:: United States

Language:: English

References (130)

System, Apparatus and Methods to Implement High-Speed Network Analyzers Ros-Giralt, Jordi; Szilagyi, Peter; Ezick, James https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100281160 US Patent Application 12/770649; 20100281160	patent-application	November 2010
Method and apparatus for using ternary and binary content-addressable memory stages to classify packets Cheriton, David R. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7002965 US Patent Document 7,002,965	patent	February 2006
A Compiler Framework for Tiling Imperfectly-Nested Loops Song, Yonghong; Li, Zhiyuan; Goos, Gerhard Languages and Compilers for Parallel Computing https://doi.org/10.1007/3-540-44905-1_12	book	January 2000
Normalised Givens rotations for recursive least squares processing McWhirter, J. G.; Walke, R. L.; Kadlec, J. VLSI Signal Processing, VIII https://doi.org/10.1109/VLSISP.1995.527503	conference	January 1995
Information management and retrieval Weeks, Richard https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6338057 US Patent Document 6,338,057	patent	January 2002
System and Method for Domain Stretching for an Advanced Dual-Representation Polyhedral Loop Transformation Framework Eichenberger, Alexandre E.; O'Brien, John K. P.; O'Brien, Kathryn M. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090307673 US Patent Application 11/861503; 20090307673	patent-application	December 2009
System and method for creating systolic solvers Cronquist, Darren Charles; Schlansker, Michael https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7086038 US Patent Document 7,086,038	patent	August 2006
Flow-insensitive interprocedural alias analysis in the presence of pointers Burke, Michael; Carini, Paul; Choi, Jong-Deok Languages and Compilers for Parallel Computing, p. 234-250 https://doi.org/10.1007/BFb0025882	book	June 2005
Array-data flow analysis and its use in array privatization Maydan, Dror E.; Amarasinghe, Saman P.; Lam, Monica S. Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '93 https://doi.org/10.1145/158511.158515	conference	January 1993
Fast and Robust Classification Algorithm for Vein Recognition Using Infrared Images Shiell, Derek; Xiao, Jing https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130268563 US Patent Application 13/443615; 20130268563	patent-application	October 2013
Adaptive transaction manager for complex transactions and business process McGoveran, David O. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20040068501 US Patent Application 10/263589; 20040068501	patent-application	April 2004
System and method for identifying matches of query patterns to document text in a document textbase Masand, Brij M. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6131092 US Patent Document 6,131,092	patent	October 2000
Maximizing parallelism and minimizing synchronization with affine transforms Lim, Amy W.; Lam, Monica S. Proceedings of the 24th ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '97 https://doi.org/10.1145/263699.263719	conference	January 1997
Polyhedral Code Generation in the Real World Vasilache, Nicolas; Bastoul, Cedric; Cohen, Albert Compiler Construction, p. 185-201 https://doi.org/10.1007/11688839_16	book	January 2006
Enabling Loop Fusion and Tiling for Cache Performance by Fixing Fusion-Preventing Data Dependences 2005 International Conference on Parallel Processing (ICPP'05) https://doi.org/10.1109/ICPP.2005.37	conference	January 2005
Fuzzy Array Dataflow Analysis Barthou, Denis; Collard, Jean-François; Feautrier, Paul Journal of Parallel and Distributed Computing, Vol. 40, Issue 2 https://doi.org/10.1006/jpdc.1996.1261	journal	February 1997
Optimal weighted loop fusion for parallel programs Megiddo, Nimrod; Sarkar, Vivek Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures - SPAA '97 https://doi.org/10.1145/258492.258520	conference	January 1997
Register tiling in nonrectangular iteration spaces Jiménez, Marta; Llabería, José M.; Fernández, Agustín ACM Transactions on Programming Languages and Systems, Vol. 24, Issue 4 https://doi.org/10.1145/567097.567101	journal	July 2002
System and method for controlling updates of a data structure Sathe, Satish; Marulkar, Rajendra; Vaishampayan, Sagar https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8898204 US Patent Document 8,898,204	patent	November 2014
The Z-polyhedral model Gupta, Gautam; Rajopadhye, Sanjay Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '07 https://doi.org/10.1145/1229428.1229478	conference	January 2007
Conversion of control dependence to data dependence Allen, J. R.; Kennedy, Ken; Porterfield, Carrie Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages - POPL '83 https://doi.org/10.1145/567067.567085	conference	January 1983
Software pipelining: an effective scheduling technique for VLIW machines Lam, M. ACM SIGPLAN Notices, Vol. 23, Issue 7 https://doi.org/10.1145/960116.54022	journal	July 1988
Sparsity in higher order methods for unconstrained optimization Gundersen, Geir; Steihaug, Trond Optimization Methods and Software, Vol. 27, Issue 2 https://doi.org/10.1080/10556788.2011.597853	journal	April 2012
Adaptively weighted, partitioned context edit distance string matching Richardson, Alvin Charles; Davis, Charles Michael; Miranker, Daniel P. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20020021838 US Patent Application 09/915603; 20020021838	patent-application	February 2002
Manufacturing cheap, resilient, and stealthy opaque constructs Collberg, Christian; Thomborson, Clark; Low, Douglas Proceedings of the 25th ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '98 https://doi.org/10.1145/268946.268962	conference	January 1998
Loop optimization with mapping code on an architecture Danckaert, Koen; Catthoor, Francky https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6772415 US Patent Document 6,772,415	patent	August 2004
System and method for performing regular expression matching with high parallelism Gai, Silvano; Malagrino, Dante https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7225188 US Patent Document 7,225,188	patent	May 2007
Network surveillance using long-term and short-term statistical profiles to determine suspicious network activity Porras, Phillip A.; Valdes, Alfonso https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7594260 US Patent Document 7,594,260	patent	September 2009
Putting Polyhedral Loop Transformations to Work Bastoul, Cédric; Cohen, Albert; Girbal, Sylvain Languages and Compilers for Parallel Computing https://doi.org/10.1007/978-3-540-24644-2_14 p. 209-225	book	January 2004
Method and apparatus for improving performance of a program using a loop interchange, loop distribution, loop interchange sequence Schooler, Richard https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6038398 US Patent Document 6,038,398	patent	March 2000
Locality manager having memory and independent code, bus interface logic, and synchronization components for a processing element for intercommunication in a latency tolerant multiple processor Casavant, Thomas L.; Fineberg, Samuel A.; Bright, Devin L. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5613136 US Patent Document 5,613,136	patent	March 1997
Real-time document collection search engine with phrase indexing Kirsch, Steven T.; Chang, William; Miller, Ed https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5920854 US Patent Document 5,920,854	patent	July 1999
Full regular expression search of network traffic Mathur, Alok; Beylin, Boris https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6952694 US Patent Document 6,952,694	patent	October 2005
Method and system for reordering the instructions of a computer program to optimize its execution Heisch, Randall Ray https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6006033 US Patent Document 6,006,033	patent	December 1999
Integrated circuit apparatus and method for high throughput signature based network applications Barrie, Robert Matthew; Gould, Stephen; Williams, Darren https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20050114700 US Patent Application 10/640870; 20050114700	patent-application	May 2005
Scanning polyhedra with DO loops Ancourt, Corinne; Irigoin, François ACM SIGPLAN Notices, Vol. 26, Issue 7 https://doi.org/10.1145/109626.109631	journal	July 1991
The program dependence graph and its use in optimization Ferrante, Jeanne; Ottenstein, Karl J.; Warren, Joe D. ACM Transactions on Programming Languages and Systems, Vol. 9, Issue 3 https://doi.org/10.1145/24039.24041	journal	July 1987
Automatic mapping of nested loops to FPGAS Ramanujam, J.; Sadayappan, P. Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '07 https://doi.org/10.1145/1229428.1229446	conference	January 2007
Some efficient solutions to the affine scheduling problem. I. One-dimensional time Feautrier, Paul International Journal of Parallel Programming, Vol. 21, Issue 5, p. 313-347 https://doi.org/10.1007/BF01407835	journal	October 1992
Whole program path profiling Larus, James R.; Fraser, Christopher W. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6327699 US Patent Document 6,327,699	patent	December 2001
Parallel Sparse Supports for Array Intrinsic Functions of Fortran 90 Chang, Rong-Guey; Chuang, Tyng-Ruey; Lee, Jenq Kuen The Journal of Supercomputing, Vol. 18, Issue 3, p. 305-339 https://doi.org/10.1023/A:1008113800183	journal	March 2001
Tiling Imperfectly-nested Loop Nests Ahmed, N.; Mateev, N.; Pingali, K. ACM/IEEE SC 2000 Conference (SC'00) https://doi.org/10.1109/SC.2000.10018	conference	January 2000
Pipelined Processor and Compiler/Scheduler for Variable Number Branch Delay Slots Van De Waerdt, Jan-Willem; Roos, Steven https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100050164 US Patent Application 12/518485; 20100050164	patent-application	February 2010
Data transformations for streaming applications on multiprocessors Liao, Shih-wei; Du, Zhaohui; Wu, Gansha https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20070074195 US Patent Application 11/234484; 20070074195	patent-application	March 2007
A Library for Doing Polyhedral Operations Wilde, Doran K. Parallel Algorithms and Applications, Vol. 15, Issue 3-4 https://doi.org/10.1080/01495730008947354	journal	December 2000
An experimental evaluation of tiling and shackling for memory hierarchy management Kodukula, Induprakas; Pingali, Keshav; Cox, Robert Proceedings of the 13th international conference on Supercomputing - ICS '99 https://doi.org/10.1145/305138.305243	conference	January 1999
Modification of swing modulo scheduling to reduce register usage Martin, Allan Russell https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060048123 US Patent Application 10/930039; 20060048123	patent-application	March 2006
Stateful packet content matching mechanisms Balakrishnan, Santosh; Ramakrishna, Venkatraman https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7784094 US Patent Document 7,784,094	patent	August 2010
Towards automatic generation of vulnerability-based signatures Brumley, D.; Newsome, J.; Song, D. 2006 IEEE Symposium on Security and Privacy (S&P'06) https://doi.org/10.1109/SP.2006.41	conference	January 2006
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor Sankaralingam, Karthikeyan; Nagarajan, Ramadass; McDonald, Robert 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06) https://doi.org/10.1109/MICRO.2006.19	conference	December 2006
Systems and Methods for Efficient Detection of Fingerprinted Data and Information Barkan, Roy; Lazarov, David; Menaker, Yevgeny https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20110035805 US Patent Application 12/786284; 20110035805	patent-application	February 2011
Background memory allocation for multi-dimensional signal processing Balasa, Florin; Catthoor, Francky; De Man, Hugo https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5742814 US Patent Document 5,742,814	patent	April 1998
Distribution of flows in a flow-based multi-processor system Sinha, Amit https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7369557 US Patent Document 7,369,557	patent	May 2008
Compiler Transformation of Pointers to Explicit Array Accesses in DSP Applications Franke, Björn; O’Boyle, Michael; Goos, Gerhard Compiler Construction https://doi.org/10.1007/3-540-45306-7_6	book	January 2001
Generation of high-performance protocol-aware analyzers with applications in intrusion detection systems Ros-Giralt, Jordi; Szilagyi, Peter; Ezick, James https://doi.org/10.1117/12.848702	conference	April 2010
Search apparatus and method using order pattern including repeating pattern Akaboshi, Naoki https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6912526 US Patent Document 6,912,526	patent	June 2005
A unified approach to global program optimization Kildall, Gary A. Proceedings of the 1st annual ACM SIGACT-SIGPLAN symposium on Principles of programming languages - POPL '73 https://doi.org/10.1145/512927.512945	conference	January 1973
Efficiently computing static single assignment form and the control dependence graph Cytron, Ron; Ferrante, Jeanne; Rosen, Barry K. ACM Transactions on Programming Languages and Systems, Vol. 13, Issue 4 https://doi.org/10.1145/115372.115320	journal	October 1991
Efficient data compression methods for multidimensional sparse array operations based on the ekmr scheme IEEE Transactions on Computers, Vol. 52, Issue 12 https://doi.org/10.1109/TC.2003.1252859	journal	December 2003
System, apparatus and methods to implement high-speed network analyzers Ezick, James; Lethin, Richard A.; Ros-Giralt, Jordi https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9185020 US Patent Document 9,185,020	patent	November 2015
Early Control of Register Pressure for Software Pipelined Loops Sid-Ahmed-Ali, Touati; Eisenbeis, Christine; Goos, Gerhard Compiler Construction https://doi.org/10.1007/3-540-36579-6_2	book	January 2003
Systems and methods for detecting malicious network content Staniford, Stuart; Aziz, Ashar https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8850571 US Patent Document 8,850,571	patent	September 2014
Intrusion detection signature analysis using regular expressions and logical operators Shanklin, Steven D.; Bernhard, Thomas E.; Lathem, Gerald S. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6792546 US Patent Document 6,792,546	patent	September 2004
System and method for optimizing operations via dataflow analysis Scales, Daniel J. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7185327 US Patent Document 7,185,327	patent	February 2007
Methods And Systems To Detect An Evasion Attack Varghese, George; Bonomi, Flavio; Fingerhut, John https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20070192861 US Patent Application 11/552025; 20070192861	patent-application	August 2007
Generation of Efficient Nested Loops from Polyhedra Quillere, Fabien; Rajopadhye, Sanjay; Wilde, Doran International Journal of Parallel Programming, Vol. 28, Issue 5, p. 469-498 https://doi.org/10.1023/A:1007554627716	journal	October 2000
Reducing Data Read Latency in a Network Communications Processor Architecture Pollock, Steven; Burroughs, William; Mital, Deepak https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20110225588 US Patent Application 12/975823; 20110225588	patent-application	September 2011
Dataflow analysis of array and scalar references Feautrier, Paul International Journal of Parallel Programming, Vol. 20, Issue 1, p. 23-53 https://doi.org/10.1007/BF01407931	journal	February 1991
Synthesizing transformations for locality enhancement of imperfectly-nested loop nests Ahmed, Nawaaz; Mateev, Nikolay; Pingali, Keshav 25th Anniversary International Conference on Supercomputing Anniversary Volume - https://doi.org/10.1145/2591635.2667179	conference	January 2014
Parallel processing of distributed arrays and optimum data distribution Luszczek, Piotr R.; Little, John N.; Martin, Jocelyn Luke https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8250550 US Patent Document 8,250,550	patent	August 2012
The mapping of linear recurrence equations on regular arrays Quinton, Patrice; van Dongen, Vincent Journal of VLSI signal processing systems for signal, image and video technology, Vol. 1, Issue 2, p. 95-113 https://doi.org/10.1007/BF02477176	journal	October 1989
Loop allocation for optimizing compilers Archambault, Roch G.; Blainey, Robert J. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6651246 US Patent Document 6,651,246	patent	November 2003
Parallel programming computing system to dynamically allocate program portions Little, John N.; Hicklin, Joseph F.; Martin, Jocelyn Luke https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8108845 US Patent Document 8,108,845	patent	January 2012
Non-literal textual search using fuzzy finite-state linear non-deterministic automata Hunter, Kenneth M. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6018735 US Patent Document 6,018,735	patent	January 2000
Method and apparatus for a generic language interface to apply loop optimization transformations Blainey, Robert James; Tal, Arie https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060048121 US Patent Application 10/926601; 20060048121	patent-application	March 2006
Precise Data Locality Optimization of Nested Loops Loechner, Vincent; Meister, Benoit; Clauss, Philippe The Journal of Supercomputing, Vol. 21, Issue 1, p. 37-76 https://doi.org/10.1023/A:1013535431127	journal	January 2002
Memory manager for heterogeneous memory control Sakarda, Premanand; Brandt, Todd; Wu, Hai Hua https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20070033367 US Patent Application 11/196959; 20070033367	patent-application	February 2007
Compiler Apparatus and Method for Optimizing Loops in a Computer Program Roediger, Robert Ralph; Schmidt, William Jon https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20030097652 US Patent Application 09992324; 20030097652	patent-application	May 2003
Value dependence graphs: representation without taxation Weise, Daniel; Crew, Roger F.; Ernst, Michael Proceedings of the 21st ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '94 https://doi.org/10.1145/174675.177907	conference	January 1994
Scalable Tensor Decompositions for Multi-aspect Data Mining Kolda, Tamara G.; Sun, Jimeng 2008 Eighth IEEE International Conference on Data Mining (ICDM) https://doi.org/10.1109/ICDM.2008.89	conference	December 2008
Bi-Directional Communication in a Parallel Processing Environment Stefansson, Halldor Narfi; Dean, Loren; Lurie, Roy https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090119677 US Patent Application 11/841861; 20090119677	patent-application	May 2009
Operator strength reduction Cooper, Keith D.; Simpson, L. Taylor; Vick, Christopher A. ACM Transactions on Programming Languages and Systems, Vol. 23, Issue 5 https://doi.org/10.1145/504709.504710	journal	September 2001
Space–time mapping and tiling: a helpful combination Griebl, Martin; Faber, Peter; Lengauer, Christian Concurrency and Computation: Practice and Experience, Vol. 16, Issue 23, p. 221-246 https://doi.org/10.1002/cpe.772	journal	January 2004
Methods and apparatus for joint parallelism and locality optimization in source code compilation Lethin, Richard A.; Leung, Allen K.; Meister, Benoit J. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8572590 US Patent Document 8,572,590	patent	October 2013
System and method for regular expression matching using index Cho, Junghoo; Rajagopalan, Sridhar https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6754650 US Patent Document 6,754,650	patent	June 2004
Variance Analysis for Translating Cuda code for Execution by a General Purpose Processor Grover, Vinod; Aarts, Bastiaan Joannes Matheus; Murphy, Michael https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090259997 US Patent Application 12/415090; 20090259997	patent-application	October 2009
Selective code generation optimization for an advanced dual-representation polyhedral loop transformation framework Eichenberger, Alexandre E.; O'Brien, John Kevin Patrick; O'Brien, Kathryn M. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8087010 US Patent Document 8,087,010	patent	December 2011
Code generation for multiple mappings Kelly, W.; Pugh, W.; Rosser, E. Proceedings Frontiers '95. The Fifth Symposium on the Frontiers of Massively Parallel Computation https://doi.org/10.1109/FMPC.1995.380437	conference	January 1994
Speculative Code Motion for Memory Latency Hiding Li, Long; Dai, Jinquan; Lv, Zhiyuan https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090037889 US Patent Application 10/582519; 20090037889	patent-application	February 2009
Constant propagation with conditional branches Wegman, Mark N.; Zadeck, F. Kenneth ACM Transactions on Programming Languages and Systems, Vol. 13, Issue 2 https://doi.org/10.1145/103135.103136	journal	April 1991
Method and system for memory management optimization Schreiber, Robert S. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20040034754 US Patent Application 10/223224; 20040034754	patent-application	February 2004
Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging Casavant, Thomas L.; Fineberg, Samuel A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5442797 US Patent Document 5,442,797	patent	August 1995
Minimum-cost network hardening Noel, Steven E.; Jajodia, Sushil; O'Berry, Brian C. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060085858 US Patent Application 11/250449; 20060085858	patent-application	April 2006
Method and Apparatus for Detecting Application Seol, Jae-Young; Rho, Sang-Ig; Lee, Ho-Cheol https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150195155 US Patent Application 14/592540; 20150195155	patent-application	July 2015
Solution and Optimization of Systems of Pseudo-Boolean Constraints Aloul, Fadi A.; Ramani, Arathi; Sakallah, Karem A. IEEE Transactions on Computers, Vol. 56, Issue 10 https://doi.org/10.1109/TC.2007.1075	journal	October 2007
Method for execution of query to search strings of characters that match pattern with a target string utilizing bit vector Fritchman, Barry Lynn https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6785677 US Patent Document 6,785,677	patent	August 2004
Blocking and array contraction across arbitrarily nested loops using affine partitioning Lim, Amy W.; Liao, Shih-Wei; Lam, Monica S. ACM SIGPLAN Notices, Vol. 36, Issue 7 https://doi.org/10.1145/568014.379586	journal	July 2001
Efficient representation scheme for multidimensional array operations IEEE Transactions on Computers, Vol. 51, Issue 3 https://doi.org/10.1109/12.990130	journal	March 2002
Systems and methods for processing data flows Kapoor, Harsh; Akerman, Moisey; Justus, Stephen D. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8010469 US Patent Document 8,010,469	patent	August 2011
Simultaneously searching for a plurality of patterns definable by complex expressions, and efficiently generating data for such searching Cheng, Paul; Chien, Fangli https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7260558 US Patent Document 7,260,558	patent	August 2007
Generating efficient parallel code using partitioning, coalescing, and degenerative loop and guard removal Liao, Shih-wei; Du, Zhao Hui; Cheng, Bu Qi https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7757222 US Patent Document 7,757,222	patent	July 2010
An Efficient Inclusion-Based Points-To Analysis for Strictly-Typed Languages Whaley, John; Lam, Monica S.; Goos, Gerhard Static Analysis https://doi.org/10.1007/3-540-45789-5_15	book	January 2002
Adaptive array beamforming with fixed-point arithmetic matrix inversion using Givens rotations Rabinkin, Daniel V.; Song, William; Vai, M. Michael https://doi.org/10.1117/12.448661	conference	November 2001
Binary state machine system and method for REGEX processing of a data stream in an intrusion detection system Carter, Earl Thomas https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6880087 US Patent Document 6,880,087	patent	April 2005
Symbolic array dataflow analysis for array privatization and program parallelization Gu, Junjie; Li, Zhiyuan; Lee, Gyungho Proceedings of the 1995 ACM/IEEE conference on Supercomputing (CDROM) - Supercomputing '95 https://doi.org/10.1145/224170.224318	conference	January 1995
On the (Im)possibility of Obfuscating Programs Barak, Boaz; Goldreich, Oded; Impagliazzo, Rusell Advances in Cryptology — CRYPTO 2001 https://doi.org/10.1007/3-540-44647-8_1	book	January 2001
Programmable packet processor with flow resolution logic Cathey, Jim; Michels, Timothy Scott https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7075926 US Patent Document 7,075,926	patent	July 2006
Cross-Product Refactoring Apparatus and Method Huang, Wei; Klicnik, Vladimir; Lo, Grace Hai Yan https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100162225 US Patent Application 12/339615; 20100162225	patent-application	June 2010
Forward Communication Only Placements and Their Use for Parallel Program Construction Griebl, Martin; Feautrier, Paul; Größlinger, Armin Languages and Compilers for Parallel Computing, p. 16-30 https://doi.org/10.1007/11596110_2	book	January 2005
Configurable string matching hardware for speeding up intrusion detection Aldwairi, Monther; Conte, Thomas; Franzon, Paul ACM SIGARCH Computer Architecture News, Vol. 33, Issue 1 https://doi.org/10.1145/1055626.1055640	journal	March 2005
The Omega test: a fast and practical integer programming algorithm for dependence analysis Pugh, William Proceedings of the 1991 ACM/IEEE conference on Supercomputing - Supercomputing '91 https://doi.org/10.1145/125826.125848	conference	January 1991
Collecting and analyzing graphical data flow web application results from multiple users Austin, Paul F.; Kudukoli, Ramprasad https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8307347 US Patent Document 8,307,347	patent	November 2012
Execution of hardware description language (HDL) programs Eng, Tommy K. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8230408 US Patent Document 8,230,408	patent	July 2012
Systems and Methods of Data Processing Using an FPGA-Implemented Hash Function Stroud, Jonathan; Cook, Brent Aaron https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130343181 US Patent Application 13/529289; 20130343181	patent-application	December 2013
A data locality optimizing algorithm Wolf, Michael E.; Lam, Monica S. ACM SIGPLAN Notices, Vol. 26, Issue 6 https://doi.org/10.1145/113446.113449	journal	June 1991
System, methods and apparatus for program optimization for multi-threaded processor architectures Bastoul, Cedric; Lethin, Richard A.; Leung, Allen K. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8930926 US Patent Document 8,930,926	patent	January 2015
Scaling to the end of silicon with EDGE architectures Burger, D.; Keckler, S. W.; McKinley, K. S. Computer, Vol. 37, Issue 7 https://doi.org/10.1109/MC.2004.65	journal	July 2004
Automatic memory layout transformations to optimize spatial locality in parameterized loop nests Clauss, Philippe; Meister, Benoît ACM SIGARCH Computer Architecture News, Vol. 28, Issue 1 https://doi.org/10.1145/346023.346031	journal	March 2000
Media for performing parallel processing of distributed arrays Luszczek, Piotr R.; Little, John N.; Martin, Jocelyn Luke https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8255890 US Patent Document 8,255,890	patent	August 2012
Method and system for memory management optimization Schreiber, Robert https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6952821 US Patent Document 6,952,821	patent	October 2005
Verifying safety properties of a class of infinite-state distributed algorithms Jonsson, Bengt; Kempe, Lars; Goos, Gerhard Computer Aided Verification https://doi.org/10.1007/3-540-60045-0_39	book	January 1995
Searching for patterns in encrypted data Arnold, William C.; Chess, David M.; Kephart, Jeffrey O. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5442699 US Patent Document 5,442,699	patent	August 1995
Fast and robust classification algorithm for vein recognition using infrared images Shiell, Derek; Xiao, Jing https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8977648 US Patent Document 8,977,648	patent	March 2015
Dynamic signature inspection-based network intrusion detection Vaidya, Vimal https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6279113 US Patent Document 6,279,113	patent	August 2001
Arrangement in a network for passing control of distributed data between network nodes for optimized client access based on locality Turner, Bryan C.; Toebes, John https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7634566 US Patent Document 7,634,566	patent	December 2009
Parallel Sparse Matrix-Matrix Multiplication and Indexing: Implementation and Experiments Buluç, Aydin; Gilbert, John R. SIAM Journal on Scientific Computing, Vol. 34, Issue 4 https://doi.org/10.1137/110848244	journal	January 2012
Two Fast Algorithms for Sparse Matrices: Multiplication and Permuted Transposition Gustavson, Fred G. ACM Transactions on Mathematical Software, Vol. 4, Issue 3 https://doi.org/10.1145/355791.355796	journal	September 1978
Method of, system for, and computer program product for minimizing loop execution time by optimizing block/tile sizes Megiddo, Nimrod; Sarkar, Vivek https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5953531 US Patent Document 5,953,531	patent	September 1999
Event Detection Method Cao, Bin; Wang, Yong https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080010680 US Patent Application 11/691155; 20080010680	patent-application	January 2008
System and Method for Advanced Polyhedral Loop Transformations of Source Code in a Compiler Eichenberger, Alexandre E.; O'Brien, John K. P.; O'Brien, Kathryn M. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090083724 US Patent Application 11/861449; 20090083724	patent-application	March 2009

Similar Records

Efficient packet forwarding using cyber-security aware policies

Patent · Wed Oct 25 00:00:00 EDT 2017 · OSTI ID:1349673

Ros-Giralt, Jordi

Forward and reverse rearrangements of dislocations in cell walls

Conference · Tue Jan 01 00:00:00 EST 1985 · OSTI ID:1349673

Hasegawa, T; Yakou, T; Kocks, U F

Approximations for second moments of performance parameters in distributed database networks

Miscellaneous · Sun Jan 01 00:00:00 EST 1989 · OSTI ID:1349673

Ronen, Y

Related Subjects

97 MATHEMATICS AND COMPUTING

Title: Efficient packet forwarding using cyber-security aware policies

Citation Formats

References (130)

Similar Records

Related Subjects