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Title: Static and Dynamic Frequency Scaling on Multicore CPUs

Journal Article · · ACM Transactions on Architecture and Code Optimization
DOI:https://doi.org/10.1145/3011017· OSTI ID:1344646
 [1];  [1];  [2];  [3];  [4];  [5];  [1]
  1. The Ohio State University, Columbus, Ohio
  2. IBM Research India, S. Cass Avenue Lemont, IL
  3. Pacific Northwest National Laboratory, Richland, WA
  4. Colorado State University, Fort Collins, CO
  5. University Grenoble Alpes, Grenoble France

Dynamic voltage and frequency scaling (DVFS) adapts CPU power consumption by modifying a processor’s operating frequency (and the associated voltage). Typical approaches employing DVFS involve default strategies such as running at the lowest or the highest frequency, or observing the CPU’s runtime behavior and dynamically adapting the voltage/frequency configuration based on CPU usage. In this paper, we argue that many previous approaches suffer from inherent limitations, such as not account- ing for processor-specific impact of frequency changes on energy for different workload types. We first propose a lightweight runtime-based approach to automatically adapt the frequency based on the CPU workload, that is agnostic of the processor characteristics. We then show that further improvements can be achieved for affine kernels in the application, using a compile-time characterization instead of run-time monitoring to select the frequency and number of CPU cores to use. Our framework relies on a one-time energy characterization of CPU-specific DVFS profiles followed by a compile-time categorization of loop-based code segments in the application. These are combined to determine a priori of the frequency and the number of cores to use to execute the application so as to optimize energy or energy-delay product, outperforming runtime approach. Extensive evaluation on 60 benchmarks and five multi-core CPUs show that our approach systematically outperforms the powersave Linux governor, while improving overall performance.

Research Organization:
Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC05-76RL01830
OSTI ID:
1344646
Report Number(s):
PNNL-SA-121775; KJ0402000
Journal Information:
ACM Transactions on Architecture and Code Optimization, Vol. 13, Issue 4; ISSN 1544-3566
Publisher:
Association for Computing Machinery
Country of Publication:
United States
Language:
English

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