Double-Precision Floating-Point Cores V1.9

Software · Sat Oct 15 00:00:00 EDT 2005

OSTI ID:1230855

Govindu, Gokul; Scrofano, Ronald

In studying the acceleration of scientific computing applications with reconfigurable hardware, such as field programmable gate arrays, one finds that many scientific applications require high-precision, floating-point arithmetic that is not innately supported in reconfigurable hardware. Consequently, we have written VDL code that describes hardware for performing double-precision (64-bit) floating-point arithmetic. From this code, it is possible for users to implement double-precision floating-point operations on FPGAs or any other hardware device to which VHDL code can be synthesized. Specifically, we have written code for four floating-point cores. Each core performs one operation: one performs addition/subtraction, one performs multiplication, one performs division, and one performs square root. The code includes parameters that determine the features of the floating-point cores, such as what types of floating-point numbers are supported and what roudning modes are supported. These parameters influence the frequency achievable by the designs as well as the chip area required for the designs. The parameters are chosen so that the floating-point cores have varyinig amounts of compliance with the industry standard for floating-point cores have varying amounts of compliance with the industry standard for floating-point arithmetic, IEEE standard 754. There is an additional parameter that determines the number of pipelining stages in the floating-point cores.

• Short Name / Acronym: DPFPC; 001916MLTPL00
• Site Accession Number: LA-CC-05-090; C05, 089
• Version: 00
• Programming Language(s): Medium: X; OS: Not Specified; Compatibility: Multiplatform
• Research Organization: Los Alamos National Laboratory (LANL), Los Alamos, NM (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: W-7405-ENG-36
• OSTI ID: 1230855
• Country of Origin: United States