skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Reader set encoding for directory of shared cache memory in multiprocessor system

Patent ·
OSTI ID:1134016
; ; ; ;

In a parallel processing system with speculative execution, conflict checking occurs in a directory lookup of a cache memory that is shared by all processors. In each case, the same physical memory address will map to the same set of that cache, no matter which processor originated that access. The directory includes a dynamic reader set encoding, indicating what speculative threads have read a particular line. This reader set encoding is used in conflict checking. A bitset encoding is used to specify particular threads that have read the line.

Research Organization:
International Business Machines Corporation, Armonk, NY (USA)
Sponsoring Organization:
USDOE
DOE Contract Number:
B554331
Assignee:
International Business Machines Corporation
Patent Number(s):
8,751,748
Application Number:
13/008,583
OSTI ID:
1134016
Country of Publication:
United States
Language:
English

References (29)

Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system patent April 1999
Eviction override for larx-reserved addresses patent April 2001
Apparatus and method for preventing cache data eviction during an atomic operation patent February 2002
System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture patent March 2002
Detecting full conditions in a queue patent October 2002
Multi-thread packet processor patent-application June 2002
Cache way prediction based on instruction base register patent-application September 2002
Fast and accurate cache way selection patent-application January 2003
Stall technique to facilitate atomicity in processor execution of helper set patent-application September 2004
Synchronization of parallel processes patent-application September 2005
Processor with cache way prediction and method thereof patent-application May 2006
Implementation of load linked and store conditional operations patent-application July 2006
Apparatus and method for sparse line write transactions patent-application February 2007
Separate data/coherency caches in a shared memory multiprocessor system patent-application July 2007
Architectural support for thread level speculative execution patent-application August 2007
Snoop Filter Directory Mechanism in Coherency Shared Memory System patent-application December 2007
Prefetch Miss Indicator for Cache Coherence Directory Misses on External Caches patent-application August 2008
Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory patent-application December 2008
Method and Apparatus for Employing Multi-Bit Register File Cells and SMT Thread Groups patent-application December 2008
System and Method for Executing Nested Atomic Blocks Using Split Hardware Transactions patent-application January 2009
Enabling Speculative State Information in a Cache Coherency Protocol patent-application March 2009
Efficient Deterministic Multiprocessing patent-application September 2009
Early header CRC in data response packets with variable gap count patent-application October 2009
Method, System and Apparatus for Reducing Memory Traffic in a Distributed Memory System patent-application November 2009
Cache control device and control method patent-application July 2010
Using Time Stamps to Facilitate Load Reordering patent-application August 2010
Hierarchical Bloom Filters for Facilitating Concurrency Control patent-application December 2010
Store Aware Prefetching for a Datastream patent-application March 2011
Bulk Disambiguation of Speculative Threads in Multiprocessors conference January 2006

Cited By (1)

Identifying performance limiting internode data sharing on NUMA platforms patent May 2016

Similar Records

Related Subjects

97 MATHEMATICS AND COMPUTING