Tuple spaces in hardware for accelerated implicit routing
- Los Alamos National Laboratory
Abstract Not Provided
- Research Organization:
- Los Alamos National Laboratory (LANL)
- Sponsoring Organization:
- DOE
- DOE Contract Number:
- AC52-06NA25396
- OSTI ID:
- 1063955
- Report Number(s):
- LA-UR-11-02785; LA-UR-11-2785
- Country of Publication:
- United States
- Language:
- English
Entering the petaflop era: The architecture and performance of Roadrunner
|
conference | November 2008 |
Generative communication in Linda
|
journal | January 1985 |
NIC-based reduction algorithms for large-scale clusters
|
journal | January 2006 |
Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs
|
journal | October 2006 |
Dynamo: amazon's highly available key-value store
|
conference | January 2007 |
Towards the measurement of tuple space performance
|
journal | December 2005 |
Hardware implementation of MPI_Barrier on an FPGA cluster
|
conference | August 2009 |
Similar Records
Tuple spaces in hardware for accelerated implicit routing
A hardware accelerator for maze routing
A Fully Implicit, Moment Accelerated, Electromagnetic Particle-in-Cell Algorithm
Journal Article
·
Tue Nov 30 23:00:00 EST 2010
·
OSTI ID:1042975
A hardware accelerator for maze routing
Journal Article
·
Sun Dec 31 23:00:00 EST 1989
· IEEE (Institute of Electrical and Electronics Engineers) Transactions on Computers; (USA)
·
OSTI ID:6996216
A Fully Implicit, Moment Accelerated, Electromagnetic Particle-in-Cell Algorithm
Conference
·
Thu Feb 20 23:00:00 EST 2014
·
OSTI ID:1121304