Serial Pixel Analog-to-Digital Converter
This method reduces the data path from the counter to the pixel register of the analog-to-digital converter (ADC) from as many as 10 bits to a single bit. The reduction in data path width is accomplished by using a coded serial data stream similar to a pseudo random number (PRN) generator. The resulting encoded pixel data is then decoded into a standard hexadecimal format before storage. The high-speed serial pixel ADC concept is based on the single-slope integrating pixel ADC architecture. Previous work has described a massively parallel pixel readout of a similar architecture. The serial ADC connection is similar to the state-of-the art method with the exception that the pixel ADC register is a shift register and the data path is a single bit. A state-of-the-art individual-pixel ADC uses a single-slope charge integration converter architecture with integral registers and “one-hot” counters. This implies that parallel data bits are routed among the counter and the individual on-chip pixel ADC registers. The data path bit-width to the pixel is therefore equivalent to the pixel ADC bit resolution.
- Research Organization:
- Nevada Test Site/National Security Technologies, LLC (United States)
- Sponsoring Organization:
- USDOE National Nuclear Security Administration (NNSA)
- DOE Contract Number:
- AC52-06NA25946
- OSTI ID:
- 1055232
- Report Number(s):
- DOE/NV/25946--861
- Journal Information:
- SPIE Proceedings, Journal Name: SPIE Proceedings Vol. 7598
- Country of Publication:
- United States
- Language:
- English
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