Critical Path-Based Thread Placement for NUMA Systems

Journal Article · Sun Jan 01 00:00:00 EST 2012 · Performance Evaluation Review

DOI:https://doi.org/10.1145/2381056.2381079· OSTI ID:1048161

Su, Chun-Yi ^[1]; Li, Dong ^[2]; Nikolopoulos, Dimitrios ^[3]; Grove, Matthew ^[1]; Cameron, Kirk W. ^[1]; de Supinski, Bronis R. ^[4]

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1. Virginia Polytechnic Institute and State University (Virginia Tech)
2. ORNL
3. FORTH-ICS
4. Lawrence Livermore National Laboratory (LLNL)

Multicore multiprocessors use Non Uniform Memory Architecture (NUMA) to improve their scalability. However,NUMA introduces performance penalties due to remote memory accesses. Without efficiently managing data layout and thread mapping to cores, scientific applications, even if they are optimized for NUMA, may suffer performance loss. In this paper, we present an algorithm that optimizes the placement of OpenMP threads on NUMA processors. By collecting information from hardware counters and defining new metrics to capture the effects of thread placement, the algorithm reduces NUMA performance penalty by minimizing the critical path of OpenMP parallel regions and by avoiding local memory resource contention. We evaluate our algorithm with NPB benchmarks and achieve performance improvement between 8.13% and 25.68%, compared to the OS default scheduling.

• Research Organization: Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
• Sponsoring Organization: Work for Others (WFO); USDOE Office of Science (SC)
• DOE Contract Number: DE-AC05-00OR22725
• OSTI ID: 1048161
• Journal Information: Performance Evaluation Review, Vol. 40, Issue 2; ISSN 0163-5999
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ALGORITHMS
COMPUTER ARCHITECTURE
ARRAY PROCESSORS
BENCHMARKS
METRICS
PERFORMANCE