D0 Silicon Upgrade: Thermal Analysis of the D0 Double Sided Ladders
A side view of the double sided ladder is shown in Figure 1. There are two types of double sided ladder; 6 chip and 9 chip. The 6 chip ladder has three SVX II chips mounted directly opposite the cooling channel and 3 chips mounted at the ladder end. The 9 chip ladder has 4 SVX II chips directly opposite the cooling channel and 5 chips at the ladder end. The power density is highest in the 6 chip ladder. All plots and calculations in this Engineering Note pertain to the 6 chip ladder with the understanding that the 9 chip temperature profile is somewhat improved over the 6 chip due to the reduced power density in the row of chips opposite the cooling channel. The two dimensional finite difference technique used for these calculations is described in DOEN 447 and will not be described here. The assumed thermal conductivity of beryllium is 190 W/m-K, and that of silicon is 149 W/m-K. The SVX II power dissipation is assumed 0.400 W. There is no cable or hybrid component power dissipation in this set of simulations. The epoxy in the glue joints consists of 2 mils thickness of thermally conductive epoxy with 0.8 W/m-K conductivity and 1 mil thickness of 0.22 W/m-K unfilled epoxy. The assumed gas temperature outboard of the bulkhead is 15 C with a convection coefficient of 5 W/m{sup 2}-K. The cooling channel temperature is 0 C. The intention of this series of simulations is to determine the optimum thickness to achieve an acceptable silicon temperature during operation of the ladder. Once the operating temperature profile is known, the temperatures within the beryllium substrates are used as input for an ANSYS* calculation of the bow of the ladder during operation. A series of calculations have been performed over the last several months in order to consider the effect of thickness, chip power, gas temperature, etc. on the temperature profile. Only the final plots are shown here in runs 660, 661, and 662. In these three plots the conditions are identical except for the beryllium substrate thickness which is 0.3/0.3, 0.4/0.4, and 0.5/0.3 bottom/top beryllium thicknesses, which are in dimensions of mm.
- Research Organization:
- Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC)
- DOE Contract Number:
- AC02-07CH11359
- OSTI ID:
- 1033276
- Report Number(s):
- FERMILAB-D0-EN-455; TRN: US1200353
- Country of Publication:
- United States
- Language:
- English
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