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DMA engine for repeating communication patterns

Patent ·
OSTI ID:1017165
 [1];  [2];  [3];  [4];  [5];  [6]
  1. Croton on Hudson, NY
  2. Mount Kisco, NY
  3. Irvington, NY
  4. Cortlandt Manor, NY
  5. Esslingen, DE
  6. Danville, CA

A parallel computer system is constructed as a network of interconnected compute nodes to operate a global message-passing application for performing communications across the network. Each of the compute nodes includes one or more individual processors with memories which run local instances of the global message-passing application operating at each compute node to carry out local processing operations independent of processing operations carried out at other compute nodes. Each compute node also includes a DMA engine constructed to interact with the application via Injection FIFO Metadata describing multiple Injection FIFOs where each Injection FIFO may containing an arbitrary number of message descriptors in order to process messages with a fixed processing overhead irrespective of the number of message descriptors included in the Injection FIFO.

Research Organization:
International Business Machines Corporation (Armonk, NY)
Sponsoring Organization:
USDOE
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
7,802,025
Application Number:
11/768,795
OSTI ID:
1017165
Country of Publication:
United States
Language:
English

References (8)

Overview of the Blue Gene/L system architecture journal March 2005
Performance evaluation of adaptive MPI
  • Huang, Chao; Zheng, Gengbin; Kalé, Laxmikant
  • Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06 https://doi.org/10.1145/1122971.1122976
conference January 2006
Synchronization, coherence, and event ordering in multiprocessors journal February 1988
Blue Gene/L advanced diagnostics environment journal March 2005
Optimization of MPI collective communication on BlueGene/L systems conference January 2005
Intel 870: a building block for cost-effective, scalable servers journal March 2002
Directory-based cache coherence in large-scale multiprocessors journal June 1990
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures journal August 2005

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