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Low latency memory access and synchronization

Patent ·
OSTI ID:1016023
 [1];  [2];  [3];  [4];  [5];  [6];  [7];  [8];  [4];  [9]
  1. Ridgefield, CT
  2. Croton On Hudson, NY
  3. Yorktown Heights, NY
  4. Mount Kisco, NY
  5. Irvington, NY
  6. Cortlandt Manor, NY
  7. Ossining, NY
  8. Brewster, NY
  9. Bedford Hills, NY
+ Show Author Affiliations
A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.
Research Organization:
International Business Machines Corporation (Armonk, NY)
Sponsoring Organization:
USDOE
DOE Contract Number:
W-7405-ENG-48
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
7,818,514
Application Number:
12/196,796
OSTI ID:
1016023
Country of Publication:
United States
Language:
English

References (3)

A prefetching technique for irregular accesses to linked data structures
  • Karlsson, M.; Dahlgren, F.; Stenstrom, P.
  • HPCA: 6th International Symposium on High-Performance Computer Architecutre, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550) https://doi.org/10.1109/HPCA.2000.824351
conference January 1999
Effective jump-pointer prefetching for linked data structures journal May 1999
Compiler-based prefetching for recursive data structures journal September 1996

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