Implications of a PIM architectural model for MPI.

Conference · Tue Jul 01 04:00:00 EDT 2003

OSTI ID:1002079

Brockman, Jay ^[1]; Kogge, Peter ^[1]; Murphy, Richard C ^[1]; Rodrigues, Arun F ^[1]; Underwood, Keith Douglas; Brightwell, Ronald Brian

---

1. University of Notre Dame, Notre Dame, IN

Memory may be the only system component that is more commoditized than a microprocessor. To simultaneously exploit this and address the impending memory wall, processing in memory (PIM) research efforts are considering ways to move processing into memory without significantly increasing the cost of the memory. As such, PIM devices may become the basis for future commodity clusters. Although these PIM devices may leverage new computational paradigms such as hardware support for multi-threading and traveling threads, they must provide support for legacy programming models if they are to supplant commodity clusters. This paper presents a prototype implementation of MPI over a traveling thread mechanism called parcels. A performance analysis indicates that the direct hardware support of a traveling thread model can lead to an efficient, lightweight MPI implementation.

• Research Organization: Sandia National Laboratories
• Sponsoring Organization: USDOE
• DOE Contract Number: AC04-94AL85000
• OSTI ID: 1002079
• Report Number(s): SAND2003-2767C
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
COMPUTER ARCHITECTURE
IMPLEMENTATION
PERFORMANCE
PROCESSING
PROGRAMMING