Thin-film chip-to-substrate interconnect and methods for making same

Patent · Tue Jan 01 00:00:00 EST 1991

OSTI ID:867707

Tuckerman, David B ^[1]

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1. Livermore, CA

Integrated circuit chips are electrically connected to a silica wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication method uses a series of masks and etching steps to form wires in a metal layer. An additive method direct laser writes or deposits very thin metal lines which can then be plated up to form wires. A quasi-additive or subtractive/additive method forms a pattern of trenches to expose a metal surface which can nucleate subsequent electrolytic deposition of wires. Low inductance interconnections on a 25 micron pitch (1600 wires on a 1 cm square chip) can be produced. The thin film hybrid interconnect eliminates solder joints or welds, and minimizes the levels of metallization. Advantages include good electrical properties, very high wiring density, excellent backside contact, compactness, and high thermal and mechanical reliability.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• DOE Contract Number: W-7405-ENG-48
• Assignee: Regents of University of California (Oakland, CA)
• Patent Number(s): US 4992847
• OSTI ID: 867707
• Country of Publication: United States
• Language: English

Related Subjects

thin-film
chip-to-substrate
interconnect
methods
integrated
circuit
chips
electrically
connected
silica
wafer
interconnection
substrate
film
wiring
fabricated
bevelled
edges
subtractive
wire
fabrication
method
series
masks
etching
steps
form
wires
metal
layer
additive
direct
laser
writes
deposits
lines
plated
quasi-additive
forms
pattern
trenches
expose
surface
nucleate
subsequent
electrolytic
deposition
inductance
interconnections
25
micron
pitch
1600
cm
square
chip
produced
hybrid
eliminates
solder
joints
welds
minimizes
levels
metallization
advantages
electrical
properties
density
excellent
backside
contact
compactness
thermal
mechanical
reliability
fabrication method
metal surface
metal layer
integrated circuit
electrically connected
electrical properties
method forms
circuit chip
metal lines
circuit chips
direct laser
electrolytic deposition
film hybrid
metal line
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