3D stacked memory
TI and LLNL demonstrated: (1) a process for the fabrication of 3-D memory using stacked DRAM chips, and (2) a fast prototyping process for 3-D stacks and MCMS. The metallization to route the chip pads to the sides of the die was carried out in a single high-speed masking step. The mask was not the usual physical one in glass and chrome, but was simply a computer file used to control the laser patteting process. Changes in either chip or customer circuit-board pad layout were easily and inexpensively accommodated, so that prototyping was a natural consequence of the laser patterning process. As in the current TI process,a dielectnc layer was added to the wafer, and vias to the chip I/O pads were formed. All of the steps in Texas Instruments earlier process that were required to gold bump the pads were eliminated, significantly reducing fabrication cost and complexity. Pads were created on the sides of the die, which became pads on the side of the stack. In order to extend the process to accommodate non-memory devices with substantially greater I/O than is required for DRAMs, pads were patterned on two sides of the memory stacks as a proof of principle. Stacking and bonding were done using modifications of the current TI process. After stacking and bonding, the pads on the sides of the dice were connected by application of a polyimide insulator film with laser ablation of the polylimide to form contacts to the pads. Then metallization was accomplished in the same manner as on the individual die.
- Research Organization:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE Office of Defense Programs (DP)
- DOE Contract Number:
- W-7405-Eng-48
- OSTI ID:
- 764028
- Report Number(s):
- UCRL-ID-140517; LLNL-TR-747185; CRADA No. TC-0494-93; OSTI ID 1426105
- Country of Publication:
- United States
- Language:
- English
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