An FPGA-based Pattern Recognition Associative Memory

Technical Report · Thu Jul 05 00:00:00 EDT 2018

DOI:https://doi.org/10.2172/1480099· OSTI ID:1480099

Olsen, Jamieson ^[1]; Liu, Tiehui Ted ^[1]; Hoff, Jim ^[1]; Hu, Zhen ^[1]; Wu, Jim -Yuan ^[1]; Xu, Zijun ^[2]

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1. Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
2. Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Peking Univ. Peking (China)

Pattern recognition associative memory (PRAM) devices are parallel processing engines which are used to tackle the complex combinatorics of track nding algorithms, particularly for silicon based tracking triggers. PRAM development has been mostly limited to the realm of ASICs, which often leads to lengthy and expensive design cycles. FPGAs allow for quick iterations, making them an ideal hardware platform for designing and evaluating new PRAM features before committing to silicon. In this paper we present our FPGA-based PRAM designs and discuss how logic blocks which were originally developed for ASICs have been redesigned to take advantage of modern FPGA architectures.

• Research Organization: Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
• Sponsoring Organization: USDOE Office of Science (SC), High Energy Physics (HEP)
• DOE Contract Number: AC02-07CH11359
• OSTI ID: 1480099
• Report Number(s): FERMILAB-TM-2681-PPD; 1699915
• Country of Publication: United States
• Language: English

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