Droop Compensation with soft Switching for High Voltage Converter Modulator (HVCM)

Conference · Mon Jun 04 00:00:00 EDT 2012

DOI:https://doi.org/10.1109/IPMHVC.2012.6518870· OSTI ID:1043000

Bland, Michael ^[1]; Scheinker, Alexander ^[2]; Clare, Jon ^[1]; Watson, Alan ^[1]; Ji, Chao ^[1]; Reass, William ^[2]

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1. University of Nottingham
2. Los Alamos National Laboratory

High Voltage Converter Modulators (HVCM) offer significant performance advantages over conventional modulator technologies for long pulse applications. One of the key advantages of HVCM technology is the ability to compensate for capacitor bank voltage droop. Achieving droop compensation without incurring significant additional switching loss has not been possible in existing designs. This paper presents an analysis of the 'Y-point' variant of the HVCM topology using the Combined Phase and Frequency Modulation (CPFM) technique. This, combined with the addition of a 'lossless' snubber circuit, enables droop compensation while achieving soft switching over the entire pulse duration. The rise time and overshoot of the output voltage pulse is optimized using an iterative extreme seeking algorithm. The optimization reduces the rise time from 100 {micro}s to 50 {micro}s with no overshoot. This will lead to an increase in overall accelerator efficiency.

• Research Organization: Los Alamos National Laboratory (LANL), Los Alamos, NM (United States)
• Sponsoring Organization: DOE/LANL
• DOE Contract Number: AC52-06NA25396
• OSTI ID: 1043000
• Report Number(s): LA-UR-12-21857; TRN: US1202983
• Resource Relation: Conference: 2012 IEEE International Power Modulator and High Voltage Conference ; 2012-06-03 - 2012-06-07 ; San Diego, California, United States
• Country of Publication: United States
• Language: English

Related Subjects

43 PARTICLE ACCELERATORS
42 ENGINEERING
ACCELERATORS
CAPACITORS
EFFICIENCY
FREQUENCY MODULATION
OPTIMIZATION
PERFORMANCE
PULSE RISE TIME
TOPOLOGY
VOLTAGE DROP