Eps'88: Combining the best features of von Neumann and dataflow computing
A new parallel architecture is presented which combines the beneficial features of both dataflow and von Neumann computers. Dynamic exploitation of parallelism is supported by a direct match dataflow scheduling mechanism. The dataflow scheduling mechanism can be applied to individual instructions or to groups of instructions. These groups of instructions are executed in a predetermined order, as in von Neumann machines. This deterministic scheduling allows the reuse of data through common memory locations and the use of local state (registers) to minimize resource requirements and latency. The foundation of this architecture includes single clock, direct matching of operands, dynamically allocated frame-based data storage, and a general repeat function that can dispatch instructions in a predetermined order. The ability to execute fully and partially ordered instruction streams makes the architecture amenable to both imperative and functional languages. The operation of the processor architecture, the associated structured memory system, proposed interconnections, and programming considerations are described. The entire architecture has been captured in a functional simulator, and hardware implementations of several of the vital parts are underway. 7 refs., 17 figs.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (USA)
- DOE Contract Number:
- AC04-76DP00789
- OSTI ID:
- 6432716
- Report Number(s):
- SAND-88-3128; ON: DE89007291
- Resource Relation:
- Other Information: Portions of this document are illegible in microfiche products
- Country of Publication:
- United States
- Language:
- English
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