Architectures for statically scheduled dataflow

Journal Article · Sat Dec 01 00:00:00 EST 1990 · Journal of Parallel and Distributed Computing; (United States)

OSTI ID:5001741

Lee, E A; Bier, J C ^[1]

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1. Univ. of California Berkeley, Berkeley, CA (US)

When dataflow program graphs can be statically scheduled, little run-time overhead (software or hardware) is necessary. This paper describes a class of parallel architectures consisting of von Neumann processors and one or more shared memories, where the order of shared- memory access is determined at compile time and enforced at run time. The architecture is extremely lean in hardware, yet for a set of important applications it can perform as well as any shared-memory architecture. Dataflow graphs can be mapped onto it statically. Furthermore, it supports shared data structures without the run-time overhead of I-structures. A software environment has been constructed that automatically maps signal processing applications onto a simulation of such an architecture, where the architecture is implemented using Motorola DSP96002 microcomputers. Static (compile-time) scheduling is possible for a subclass of dataflow program graphs where the firing pattern of actors is data independent. This model is suitable for digital signal processing and some other scientific computation. It supports recurrences, manifest iteration, and conditional assignment. However, it does not support true recursion, data-dependent iteration, or conditional evaluation. An effort is under way to weaken the constraints of the model to determine the implications for hardware design.

• OSTI ID: 5001741
• Journal Information: Journal of Parallel and Distributed Computing; (United States), Vol. 10:4; ISSN 0743-7315
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
DATA-FLOW PROCESSING
COMPUTER ARCHITECTURE
COMPUTER CODES
DESIGN
DIGITAL COMPUTERS
ITERATIVE METHODS
MEMORY MANAGEMENT
MICROPROCESSORS
PARALLEL PROCESSING
SIMULATION
COMPUTERS
ELECTRONIC CIRCUITS
MICROELECTRONIC CIRCUITS
PROGRAMMING
990200* - Mathematics & Computers